PI6C485352 Datasheet, PDF (1/7 Pages) Pericom Semiconductor Corporation – 2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer

PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential
LVPECL Clock Multiplexer
Features
ÎÎPin-to-pin compatible to ICS85352I
ÎÎFMAX ≤ 500 MHz
ÎÎPropagation Delay < 4ns
ÎÎOutput-to-output skew < 100ps
ÎÎ12 pairs of differential LVPECL outputs
ÎÎSelectable differential CLK and /CLK inputs
ÎÎCLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and
HCSL input level
ÎÎSelect input accept CMOS/LVTTL levels
ÎÎ2.5V/3.3V power supply
ÎÎOperating Temperature: -40°C to +85°C
ÎÎPackaging (Pb-free & Green):
— 48-pin TQFP (FA)
Description
The PI6C485352 is a high-performance low-skew LVPECL
fanout buffer. PI6C485352 features two selectable differential
inputs and translates to twelve LVPECL output pairs. The inputs
can also be configured to single-ended with external resistor
bias circuit. The CLK input accepts LVPECL, LVDS, LVHSTL,
SSTL or HCSL signals. The PI6C485352 is ideal for differential
to LVPECL translations and/or LVPECL clock distribution.
Typical clock translation and distribution applications are data-
communications and telecommunications.
Applications
ÎÎNetworking systems including switches and Routers
ÎÎHigh frequency backplane based computing and telecom
platforms
Block Diagram
Pin Configuration (48-Pin TQFP)
SEL [0:11]
CLK0
/CLK0
CLK1
/CLK1
12
0
1
0
1
48 47 46 45 44 43 42 41 40 39 38 37
Q0 1
36 ^Q6
/Q0 2
35 ^/Q6
Q1 3
34 ^Q7
/Q1 4
33 ^/Q7
Q0
Q2 5
/Q0
/Q2 6
32 ^Q8
31 ^/Q8
Q3 7
30 ^Q9
/Q3 8
29 ^/Q9
Q4 9
28 ^Q10
/Q4 10
27 ^/Q10
Q11
Q5 11
26 Q11
/Q11
/Q5 ¹²
25 _/Q11
13 14 15 16 17 18 19 20 21 22 23 24
13-0003
1
PI6C485352 Rev. A
01/24/13