PI6C48533-01_15 Datasheet, PDF (1/7 Pages) Pericom Semiconductor Corporation – 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer

PI6C48533-01
3.3V Low Skew 1-to-4
Differential/LVCMOS to LVPECL Fanout Buffer
Features
• Pin-to-pin compatible to ICS8533-01
• Maximum operation frequency: 800MHz
• 4 pair of differential LVPECL outputs
• Selectable differential CLK and PCLK inputs
• CLK, _nCLK pair accepts LVDS, LVPECL, LVHSTL,
SSTL and HCSL input level
• PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
• Output Skew: 100ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V power supply
• Operating Temperature: -40^oC to 85^oC
• Packaging(Pb-free & Green avaliable):
-20-pin TSSOP (L)
Description
The PI6C48533-01 is a high-performance low-skew LVPECL fanout
buffer. PI6C48533-01 features two selectable differential inputs and
translates to four LVPECL ultra-low jitter outputs.The inputs can
also be configured to single-ended with external resistor bias circuit.
The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or
HCSL signals, and PCLK input accepts LVPECL or SSTL or CML
signals.The outputs are synchronized with input clock during asyn-
chronous assertion/deassertion of CLK_EN pin.PI6C48533-01 is
ideal for differential to LVPECL translations and/or LVPECL clock
distribution.Typical clock translation and distribution applications
are data-communications and telecommunications.
Block Diagram
CLK_EN
CLK
nCLK
PCLK
nPCLK
D
Q
LE
0
1
CLK_SEL
Pin Diagram
V_EE 1
CLK_EN 2
CLK_SEL 3
Q₀
nQ0
CLK 4
n^CLK 5
Q1
PCLK 6
nQ1
n^PCLK 7
Q2
NC 8
nQ2
NC 9
Q3
V_CC 10
nQ3
20 Q₀
19 _nQ₀
18 V_CC
17 Q₁
16 _nQ₁
15 Q₂
14 _nQ₂
13 V_CC
12 Q₃
11 _nQ₃
15-0084
1
Rev B
6/23/2015