PI6C485311WE Datasheet, PDF (1/6 Pages) Pericom Semiconductor Corporation – 3.3V Low Skew 1-to-2 Differential to LVPECL Fanout Buffer

Features
• Pin-to-pin compatible to ICS85311
• Maximum operation frequency: 800MHz
• 2 pair of differential LVPECL outputs
• CLK, _nCLK pair accepts LVDS, LVPECL, LVHSTL,
SSTL and HCSL input level
• Output Skew: 100ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V power supply
• Operating Temperature: -40^oC to 85^oC
• Packaging (Pb-free & Green avaliable):
- 8-pin SOIC (W)
PI6C485311
3.3V Low Skew 1-to-2
Differential to LVPECL Fanout Buffer
Description
The PI6C485311 is a high-performance low-skew LVPECL fanout
buffer. PI6C485311 features two selectable differential inputs and
translates to four LVPECL ultra-low jitter outputs. The inputs
can also be configured to single-ended with external resistor bias
circuit. The CLK input accepts LPECL or LVDS or LVHSTL or
SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL
or CML signals. PI6C485311 is ideal for differential to LVPECL
translations and/or LVPECL clock distribution. Typical clock
translation and distribution applications are data-communications
and telecommunications.
Block Diagram
CLK
nCLK
Pin Diagram
Q0
nQ0
Q0 1
8 VCC
nQ0 2
7 CLK
Q1
Q1 3
6 nCLK
nQ1
nQ1 4
5 VEE
06-0283
1
PS8865D
11/14/06