PI6C3991 Datasheet, PDF (1/11 Pages) Pericom Semiconductor Corporation – 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock

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3.3V High-Speed, Low-Voltage
Programmable Skew Clock Buffer
SuperClock^®
Features
• All output pair skew <100ps typical (250 Max.)
• 3.75 MHz to 80 MHz output operation
• User-selectable output functions
— Selectable skew to 18ns
— Inverted and Non-Inverted
— Operation at ½ and ¼ input frequency
— Operation at 2X and 4X input frequency
(input as low as 3.75 MHz, x4 operation)
• Zero input-to-output delay
• 50% duty-cycle outputs
• LVTTL outputs drive 50-ohm terminated lines
• Operates from a single 3.3V supply
• Low operating current
• Available in 32-pin PLCC (J) package
• Jitter < 200ps peak-to-peak (< 25ps RMS)
Logic Block Diagram
Description
PI6C3991 offers selectable control over system clock functions.
These multiple-output clock drivers provide the system integrator
with functions necessary to optimize the timing of high-perfor-
mance computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated trans-
mission lines with impedances as low as 50 ohms while delivering
minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow
distribution of a low-frequency clock that can be multiplied by
two or four at the clock destination. This feature allows flexibility
and simplifies system timing distribution design for complex
high-speed systems.
Pin Configuration
Test
FB
REF
Phase
Freq.
DET
Filter
VCO and
Time Unit
Generator
FS
4F0
4Q0
4F1
4Q1
Select Inputs
(three level)
3F0
Skew
3Q0
3F1
Select
3Q1
2F0
2Q0
2F1
Matrix
2Q1
1F0
1Q0
1F1
1Q1
3F1
4F0
4F1
V_CCQ
V_CCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5
29
6
28
7
27
8
32-Pin
26
9
25
10
J
24
11
23
12
22
13
21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
V_CCN
1Q0
1Q1
GND
GND
1
PS8450B 04/09/01