PI6C2510AL Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – Phase-Lock Loop Clock Driver with 10-Clock Outputs

PI6C2510A
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Phase-Lock Loop Clock Driver
with 10-Clock Outputs
Features
• High-Performance Phase-Lock Loop Clock Distribution that
meets 100/134 MHz Registered DIMM Synchronous DRAM
modules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation for
EMI reduction
• Zero Input-to-Output delay: Distribute One Clock Input
to one bank of ten outputs, with an output enable.
• Same pinout as TI CDC2510/2510A
• Low jitter: Cycle-to-Cycle jitter ±100ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V V_CC
• Wide Clock Frequency Range:
• Packaging
-24-pin TSSOP (L)
Description
The PI6C2510A family is a low-skew, low-jitter, phase-lock loop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing one clock input to one bank of ten outputs,
with an output enable.
The PI6C2510A is designed to meet PC100 SDRAM Registered
DIMM Specification, for heavy load applications. For test pur-
poses, the PLL can be bypassed by strapping AV_CC to ground.
The PI6C2510A family has the same pinouts as TI’s CDC2510A/
2510B, with enhanced rise/fall times, and allowing a Spread Spec-
trum clock input.
Logic Block Diagram
G
CLK_IN
PLL
FB_IN
AV_CC
Product Pin Configuration
10
1Y[0:9]
FB_OUT
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FB_OUT
1
24
2
23
3
22
4
21
5
20
6
24-Pin
L
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK_IN
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FB_IN
Functional Table
Inputs
G
CLK_IN
X
L
L
H
H
H
Outputs
1Y[0:9]
FB_OUT
L
L
L
H
H
H
08-0298
1
PS8306C
11/13/08