PI6C2510-133E Datasheet, PDF (1/4 Pages) Pericom Semiconductor Corporation – Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that
meets 133 MHz Registered DIMM Synchronous DRAM mod-
ules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V VCC, 0–85°C
• Packages (Pb-free & Green available):
– Plastic 24-pin TSSOP (L)
PI6C2510-133E
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
Description
The PI6C2510-133E is a “enhanced,” low-skew, low-jitter,
phase-locked loop (PLL) clock driver, distributing high-
frequency clock signals for SDRAM and server applications. By
connecting the feedback FB_OUT output to the feedback FB_IN
input, the propagation delay from the CLK_IN input to any
clock output will be nearly zero. This zero-delay feature allows
the CLK_IN input clock to be distributed, providing one clock
input to one bank of ten outputs, with an output enable.
This clock driver is designed to meet the PC133 SDRAM
Registered DIMM specification. For test purposes, the PLL can
be bypassed by strapping AVCC to ground.
Block Diagram
G
CLK_IN
PLL
FB_IN
AVcc
Pin Configuration
10
Y[0:9]
FB_OUT
AGND 1
24 CLK_IN
V_CC 2
23 AV_CC
Y0 3
22 V_CC
Y1 4
21 Y9
Y2
GND
GND
5
6
7
24-Pin
L
20
19
18
Y8
GND
GND
Y3 8
17 Y7
Y4 9
16 Y6
V_CC 10
15 Y5
G 11
14 V_CC
FB_OUT 12
13 FB_IN
Functional Table
Inputs
G
L
H
Outputs
Y[0:9]
FB_OUT
L
CLK_IN
CLK_IN
CLK_IN
07-0199
1
PS8505B
08/30/07