PI6C2509-133 Datasheet, PDF (1/4 Pages) Pericom Semiconductor Corporation – Low-Noise Phase-Locked Loop Clock Driver with 9 Clock Outputs

PI6C2509-133
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Low-Noise Phase-Locked Loop
Clock Driver with 9 Clock Outputs
Product Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution to meet
133 MHz Registered DIMM Synchronous DRAM module
specifications for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Zero Input-to-output delay: Distribute One Clock Input to
one bank of five and one bank of four outputs, with
separate output enables
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V V_CC
• Package: Plastic 24-pin TSSOP (L)
Product Description
The PI6C2509-133 is a “quiet,” low-skew, low-jitter, phase-locked
loop (PLL) clock driver, distributing low-noise clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing 5 clocks for the first bank, and an additional
4 clocks for the second bank.
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AV_CC to ground.
Logic Block Diagram
1G
2G
CLK_IN
PLL
FB_IN
AVCC
5
1Y[0:4]
4
2Y[0:3]
FB_OUT
Product Pin Configuration
AGND
V_CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V_CC
1G
FB_OUT
1
24
2
23
3
22
4 _24-Pin 21
5
6
L
20
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK_IN
AV_CC
V_CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V_CC
2G
FB_IN
1
PSXXXX
06/01/99