PI6C2501 Datasheet, PDF (1/4 Pages) Pericom Semiconductor Corporation – Phase-Locked Loop Clock Driver

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Phase-Locked Loop Clock Driver
Product Features
• High-Performance, Phase-Locked-Loop Clock Distribution
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Zero Input-to-Output delay
• Low jitter: Cycle-to-Cycle jitter ±100ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V V_CC
• Wide range of Clock Frequencies up to 80 MHz
• Package: Plastic 8-pin SOIC (W)
Product Description
The PI6C2501 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the CLK_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to CLK_OUT output will be nearly zero.
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers, such as the
PI6C2509Q, or PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends using a zero-delay buffer and
an eighteen output non-zero-delay buffer. As shown in Figure 1,
this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Logic Block Diagram
Product Pin Configuration
CLK_IN
PLL
FB_IN
AV_CC
CLK_OUT
AGND 1
GND 2
CLK_OUT ₃
VCC 4
8-Pin
W
8 CLK_IN
7 AVCC
6 GND
5 FB_IN
Feedback
C
Zero Delay _{CLK_OUT} 18 Outputs
Buffer
Non-PLL
PI6C2501
Buffer
17
Reference
Clock
Signal
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clock Signal and 17 Outputs
1
PS8381A 07/17/00