PI6C2409-1H Datasheet, PDF (1/8 Pages) Pericom Semiconductor Corporation – Zero-Delay Clock Buffer

Features
• Maximum rated frequency: 133 MHz
• Low cycle-to-cycle jitter
• Input to output delay, less than 200ps
• Internal feedback allows outputs to be synchronized to the
clock input
• Spread spectrum compatible
• Operates at 3.3V V_DD
• Space-saving Package: (Pb-free & Green available)
- 16-Pin TSSOP(L)
- 16-Pin SOIC(W)
PI6C2409-1H
Zero-Delay Clock Buffer
Description
The PI6C2409-1H is a PLL based, zero-delay buffer, with the ability
to distribute nine outputs of up to 133 MHz at 3.3V.
All the outputs are distributed from a single clock input CLKIN and
output OUT0 performs zero delay by connecting a feedback to PLL.
PI6C2409-1H has two banks of four outputs that can be controlled by
the selection inputs, SEL1 & SEL2. It also has a power sparing feature:
when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all
outputs are referenced from CLKIN. PI6C2409-1H is available in
high drive and industrial environment versions.
An internal feedback on OUT0 is used to synchronize the
outputs to the input; the relationship between loadingof this signal
and the outputs determines the input-output delay.
PI6C2409-1H are characterized for both commercial and
industrial operation
Block Diagram
CLKIN
PLL
MUX
SEL1
SEL2
Decode
Logic
PI6C2409-1H
Pin Configuration
OUT0
OUTA1
OUTA2
OUTA3
OUTA4
OUTB1
OUTB2
OUTB3
OUTB4
CLKIN
OUTA1
OUTA2
VDD
GND
OUTB1
OUTB2
SEL2
1
16
2
15
3
14
4 16-Pin 13
5 ^{W, L} 12
6
11
7
10
8
9
OUT0
OUTA4
OUTA3
VDD
GND
OUTB4
OUTB3
SEL1
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15-0174
1
www.pericom.com 12/02/15