PI6C2408 Datasheet, PDF (1/10 Pages) Pericom Semiconductor Corporation – Zero-Delay Clock Buffer

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Zero-Delay Clock Buffer
Features
• Maximum rated frequency: 140 MHz
• Low cycle-to-cycle jitter
• Input to output delay, less than 150ps
• External feedback pin allows outputs to be synchronized
to the clock input
• 5V tolerant input*
• Operates at 3.3V V_DD
• Test mode allows bypass of the PLL for system testing
purposes (e.g., IBIS measurements)
• Clock frequency multipliers ½x to 4x dependent on option
• Packaging (Pb-free and Green available):
-16-pin, 150-mil SOIC (W)
-16-pin 173-mil TSSOP (L)
* FB_IN and CLKIN must reference the same voltage thresh-
olds for the PLL to deliver zero delay skewing
Block Diagram
FB_IN
CLKIN
÷2 _PLL
Option (-3, -4)
SEL1
SEL2
Decode
Logic
MUX
÷2
Option (-2, -3)
PI6C2408 (-1, -1H, -2, -3, -4)
FB_IN
CLKIN
PLL
MUX
SEL2
SEL1
Decode
Logic
PI6C2408-6
÷2
MUX
OUTA1
OUTA2
OUTA3
OUTA4
OUTB1
OUTB2
OUTB3
OUTB4
OUTA1
OUTA2
OUTA3
OUTA4
OUTB1
OUTB2
OUTB3
OUTB4
Description
The PI6C2408 is a PLL-based, zero-delay buffer, with the ability
to distribute eight outputs of up to 140 MHz at 3.3 V. Two banks of
four outputs exist, and, depending on product option ordered, can
supply either reference frequency, prescaled half frequency, or
multiplied 2x or 4x input clock frequencies. The PI6C2408 family has
a power-sparing feature: when input SEL2 is 0, the component will
3-state one or both banks of outputs depending on the state of input
SEL1. A PLL bypass test mode also exists. This product line is
available in high-drive and industrial environment versions.
An external feedback pin is used to synchronize the outputs to the
input; the relationship between loading of this signal and the other
outputs determines the input-output delay.
The PI6C2408 is characterized for both commercial and industrial
operation.
Pin Configuration
CLKIN
OUTA1
OUTA2
VDD
GND
OUTB1
OUTB2
SEL2
1
16
2
15
3
14
4 ^16-Pin 13
5 ^{W, L} 12
6
11
7
10
8
9
FB_IN
OUTA4
OUTA3
VDD
GND
OUTB4
OUTB3
SEL1
1
PS8589E 09/15/04