PI6C2402 Datasheet, PDF (1/4 Pages) Pericom Semiconductor Corporation – Phase-Locked Loop Clock Driver

PI6C2402
Phase-Locked Loop Clock Driver
Features
• Clock doubler
• High-Performance Phase-Locked-Loop Clock Distribution for
Networking, ATM, 100 MHz and 134 MHz Registered DIMM
Synchronous DRAM modules for server, workstation, and PC
applications
• Zero Input-to-Output delay
• Cycle-to-Cycle jitter ≤ ±150ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V V_CC
• Packaging (Pb-free & Green available):
— 8-pin SOIC Package (W)
Description
The PI6C2402 features a low-skew, low-jitter, Phase-Locked Loop
(PLL) clock driver. By connecting the feedback CLK_OUT out-
put to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero. The PI6C2402
provides 2X CLK_IN on CLK_OUT output.
Applications
If the system designer needs more than 16 outputs with the fea-
tures just described, using two or more zero-delay buffers such
as the PI6C2509, and the PI6C2510, are likely to be impractical.
The device-to-device skew introduced can significantly reduce
the performance. Pericom recommends the use of a zero-delay
buffer and an eighteen output non-zero-delay buffer. As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Block Diagram
Pin Configuration
CLK_IN
PLL
FB_IN
÷2
S
CLK_OUT
CLK_IN 1
AVCC ₂
AGND 3
CLK_OUT ₄
8 FB_IN
7 VCC
6 GND
5S
Feedback
Reference
Clock
Signal
Zero Delay _{CLK_OUT}
Buffer
PI6C2402
18 Output
Non-Zero
Delay
Buffer
Figure 1. Zero-Delay Buffering Diagram
Control Input
S
HIGH
LOW
17
Outputs Source
PLL
CLK_IN
PLL Shutdown
Disabled
Enabled
08-0298
1
PS8418I
11/13/08