PI6C2308 Datasheet, PDF (1/10 Pages) Pericom Semiconductor Corporation – 3.3V Zero-Delay Buffer

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3.3V Zero-Delay Buffer
Product Features
• 10 MHz to 134 MHz operating range
• Zero input-output propagation delay, adjustable by external
capacitive load on FBK input
• Multiple configurations, see “Available PI6C2308
Configurations” table
• Input to output delay, less than 200ps
• Multiple low skew outputs
- Output-output skew less than 200ps
- Device-device skew less than 600ps
- Two banks of four outputs, Hi-Z by two select inputs
• Low Jitter, less than 200ps
• 3.3V operation
• Space-saving Packages:
16-pin, 150-mil SOIC package (W16) (-1, -1H, -2, -3, -4, -6)
16-pin TSSOP package (L16) (-1, -1H)
• Available in industrial and commercial temperatures
Block Diagrams
REF
÷2
PLL
Extra Divider (-3, -4)
S2
Select Input
S1
Decoding
MUX
÷2
Extra Divider (-2,-3)
PI6C2308 (-1, -1H, -2, -3, -4)
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Functional Description
Providing two banks of four outputs, the PI6C2308 is a 3.3V zero-
delay buffer designed to distribute clock signals in applications
including PC, workstation, datacom, telecom, and high-performance
systems. Each bank of four outputs can be controlled by the select
inputs as shown in the Select Input Decoding Table.
The PI6C2308 provides 8 copies of a clock signal that has 200ps
phase error compared to a reference clock. The skew between the
output clock signals for PI6C2308 is less than 200ps. When there
are no rising edges on the REF input, the PI6C2308 enters a power
down state. In this mode, the PLL is off and all outputs are Hi-Z.
This results in less than 12µA of current draw. The Select Input
Decoding Table shows additional examples when the PLL shuts
down. The PI6C2308 configuration table shows all available devices.
The base part, PI6C2308-1, provides output clocks in sync with a
reference clock. With faster rise and fall times, the PI6C2308-1H
is the high drive version of the PI6C2308-1. Depending on which
output drives the feedback pin, PI6C2308-2 provides 2X and 1X
clock signals on each output bank. The PI6C2308-3 allows the user
to obtain 4X and 2X frequencies on the outputs. The PI6C2308-4
provides 2X clock signals on all outputs. PI6C2308 (-1, -2, -3, -4) allows
bank B to be Hi-Z when all output clocks are not required.The
PI6C2308-6 allows bank B to switch from Reference clock to half
of the frequency of Reference clock using the control inputs S1 and
S2 if Bank A is connected to feedback FBK. In addition, using the
control inputs S1 and S2, the PI6C2308-6 allows bank A to switch
from Reference clock to 2X the frequency of Reference clock if
Bank B is connected to feedback FBK. For testing purposes, the
select inputs connect the input clock directly to outputs.
REF
PLL
MUX
S2 _{Select Input}
S1 ^Decoding
÷2
MUX
PI6C2308-6
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Pin Configuration PI6C2308 (–1, –1H, –2, –3, –4, –6)
REF 1
CLKA1 2
CLKA2 3
V_DD 4
GND 5
CLKB1 6
CLKB2 7
S2 8
16
15
14
16-Pin ₁₃
W, L ₁₂
11
10
9
FBK
CLKA4
CLKA3
V_DD
GND
CLKB4
CLKB3
S1
1
PS8384D 06/26/01