PI6C21200AEX Datasheet, PDF (1/14 Pages) Pericom Semiconductor Corporation – 1 12 Clock Driver for Intel PCIe Chipsets

PI6C21200
1:12 Clock Driver for Intel PCIe® Chipsets
Features
• Twelve Pairs of PCIe® Differential Clocks (HCSL compatible
signaling)
• Low skew < 50ps
• Low jitter < 50ps
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fan out operation
• Gear Ratio supporting different output frequencies
• 3.3V Operation
• 56-pin Package (Pb-Free & Green):
- TSSOP (A56)
Description
PI6C21200 is a high-speed, low-noise PCIe® differential
clock buffer designed to be a companion with PI6C410B clock
synthesizer. The device distributes twelve copies of the
differential SRC clock coming from PI6C410B. The output
frequency can be ratioed to offer a derivative frequency from
the input frequency. Each differential output is controlled by
individual OE pin, except OUT10 and OUT11 are sharing one
OE_10#_11# pin. The clock outputs are controlled by input selec-
tion of SA_0, SA_1, SA_2 via SMBus, SCLK and SDA.
Block Diagram
OE [0:10]#
VTT_PWRGD#
/ PWRDWN
SCLK
SDA
SA_[0:1]
SA_2 /
PLLBypass#
SRC
SCR#
Output
Control
SMBus
Controller
HIGH_BW#
PLL
Pinout Diagram
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
OUT4
OUT4#
OUT5
OUT5#
OUT6
OUT6#
OUT7
OUT7#
OUT8
OUT8#
OUT9
OUT9#
OUT10
OUT10#
OUT11
OUT11#
HIGH_BW# 1
SRC_IN 2
SRC_IN# 3
SA_0 4
OE_0# 5
OUT0 6
OUT0# 7
OE_1# 8
OUT1 9
OUT1# 10
VDD 11
VSS 12
OUT2 13
OUT2# 14
OE_2# 15
OUT3 16
OUT3# 17
OE_3# 18
OUT4 19
OUT4# 20
OE_4# 21
VDD 22
VSS 23
OUT5 24
OUT5# 25
OE_5# 26
SA_1 27
SDA 28
56 VDD_A
55 VSS_A
54 IREF
53 OE_10#_11#
52 OUT11
51 OUT11#
50 VDD
49 VSS
48 OUT10
47 OUT10#
46 FS_A
45 VTT_PWRGD# / PWRDWN
44 OE_9#
43 OUT9
42 OUT9#
41 OE_8#
40 OUT8
39 OUT8#
38 VDD
37 VSS
36 OUT7
35 OUT7#
34 OE_7#
33 OUT6
32 OUT6#
31 OE_6#
30 SA_2 /PLLBypass#
29 SCL
09-0003
1
PS8820B
10/14/09