PI6C20800S Datasheet, PDF (1/10 Pages) Pericom Semiconductor Corporation – PCI Express 1:8 HCSL Clock Buffer

Features
• Phase jitter filter for PCIe application
• Eight Pairs of Differential Clocks
• Low skew < 50ps
• Low Cycle-to-cycle jitter < 50ps
• Output Enable for all outputs
• Outputs Tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• Packaging (Pb-Free & Green):
— 48-Pin SSOP (V)
— 48-Pin TSSOP (A)
Block Diagram
OE_INV
OE [0:7]
SRC_STOP#
PWRDWN#
SCLK
SDA
PLL/BYPASS#
SRC_DIV#
SRC
SRC#
Output
Control
SMBus
Controller
DIV
PLL_BW#
PLL
PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Description
PI6C20800S is a PCI Express, high-speed, low-noise differential
clock buffer designed to be a companion to PI6C410BS PCI
Express clock generator for Intel server chipsets. The device
distributes the differential SRC clock from PI6C410BS to eight
differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is
LOW. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is LOW, the output
clocks are Tristated. When PWRDWN# is LOW, the SDA and
SCLK inputs must be Tristated.
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
OUT4
OUT4#
OUT5
OUT5#
OUT6
OUT6#
OUT7
OUT7#
LOCK
Pin Configuration
SRC_DIV# 1
V_DD 2
VSS 3
SRC 4
SRC# 5
OE_0 6
OE_3 7
OUT0 8
OUT0# 9
VSS 10
V_DD 11
OUT1 12
OUT1# 13
OE_1 14
OE_2 15
OUT2 16
OUT2# 17
V_SS 18
VDD 19
OUT3 20
OUT3# 21
PLL/BYPASS# 22
SCLK 23
SDA 24
48 V_{DD_A}
47 V_{SS_A}
46 I_REF
45 LOCK
44 OE_7
43 OE_4
42 OUT7
41 OUT7#
40 OE_INV
39 V_DD
38 OUT6
37 OUT6#
36 OE_6
35 OE_5
34 OUT5
33 OUT5#
32 V_SS
31 V_DD
30 OUT4
29 OUT4#
28 PLL_BW#
27 SRC_STOP#
26 PWRDWN#
25 V_SS
07-0237
1
PS8887B
10/19/07