PI6C20400S Datasheet, PDF (1/10 Pages) Pericom Semiconductor Corporation – 1 4 Clock Driver for Intel PCI Express Chipsets

Features
• Phase jitter filter for PCIe Gen II application
• Four Pairs of Differential Clocks
• Low skew < 50ps
• Low jitter < 50ps cycle-to-cycle
• < 1 ps additive RMS phase jitter
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Programmable PLL Bandwidth
• 100 MHz PLL Mode operation
• 100 - 400 MHz Bypass Mode operation
• 3.3V Operation
• Packaging (Pb-free and Green):
— 28-Pin SSOP (H28) & 28-Pin TSSOP (L28)
PI6C20400S
1:4 Clock Driver for Intel
PCI Express Chipsets
Description
Pericom Semiconductor's PI6C20400S is a PCI Express GenII
compliant high-speed, low-noise differential clock buffer designed
to be companion to PI6C410BS. The device distributes the
differential SRC clock from PI6C410BS to four differential pairs
of clock outputs either with or without PLL. The clock outputs
are controlled by input selection of SRC_STOP#, PWRDWN#
and SMBus, SCLK and SDA. When input of either SRC_STOP#
or PWRDWN# is low, the output clocks are Tristated. When
PWRDWN# is low, the SDA and SCLK inputs must be Tri-
stated.
Block Diagram
OE_INV
OE_0 & OE_3
SRC_STOP#
PWRDWN#
SCLK
SDA
PLL/BYPASS#
SRC
SRC#
Output
Control
SMBus
Controller
DIV
PLL_BW#
PLL
Pin Configuration
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
VDD 1
SRC 2
SRC# 3
V_SS 4
VDD 5
OUT0 6
OUT0# 7
OE_0 8
OUT1 9
OUT1# 10
V_DD 11
PLL/BYPASS# 12
SCLK 13
SDA 14
28 V_{DD_A}
27 V_{SS_A}
26 I_REF
25 OE_INV
24 V_DD
23 OUT3
22 OUT3#
21 OE_3
20 OUT2
19 OUT2#
18 V_DD
17 PLL_BW#
16 SRC_STOP#
15 PWRDWN#
07-0265
1
PS8931A
12/10/07