PI6C20400B Datasheet, PDF (1/11 Pages) Pericom Semiconductor Corporation – 1 4 Clock Driver for Intel PCIe® 3.0 Chipsets

Features
ÎÎPhase jitter filter for PCIe 3.0 application
ÎÎFour Pairs of Differential Clocks
ÎÎLow skew < 50ps
ÎÎLow jitter < 50ps cycle-to-cycle
ÎÎ< 1 ps additive RMS phase jitter
ÎÎOutput Enable for all outputs
ÎÎOutputs tristate control via SMBus
ÎÎProgrammable PLL Bandwidth
ÎÎ100 MHz PLL Mode operation
ÎÎ100 - 400 MHz Bypass Mode operation
ÎÎ3.3V Operation
ÎÎPackaging (Pb-free and Green):
-28-Pin SSOP (H28)
-28-Pin TSSOP (L28)
Block Diagram
PI6C20400B
1:4 Clock Driver for Intel PCIe® 3.0 Chipsets
Description
Pericom Semiconductor's PI6C20400B is a PCIe 3.0 compliant
high-speed, low-noise differential clock buffer designed to be
companion to PCIe 3.0 clock generator. It is backward compat-
ible with PCIe 1.0 and 2.0 specification.
The device distributes the differential SRC clock from PCIe 3.0
clock generator to four differential pairs of clock outputs either
with or without PLL. The clock outputs are controlled by input
selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and
SDA. When input of either SRC_STOP# or PWRDWN# is low,
the output clocks are Tristated. When PWRDWN# is low, the
SDA and SCLK inputs must be Tri-stated.
Pin Configuration
OE_INV
OE_0 & OE_3
SRC_STOP#
PWRDWN#
SCLK
SDA
PLL/BYPASS#
SRC
SRC#
Output
Control
SMBus
Controller
DIV
PLL_BW#
PLL
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
VDD 1
SRC 2
SRC# 3
VSS 4
VDD 5
OUT0 6
OUT0# 7
OE_0 8
OUT1 9
OUT1# 10
VDD 11
PLL/BYPASS# 12
SCLK 13
SDA 14
28 V_{DD_A}
27 V_{SS_A}
26 I_REF
25 OE_INV
24 V_DD
23 OUT3
22 OUT3#
21 OE_3
20 OUT2
19 OUT2#
18 V_DD
17 PLL_BW#
16 SRC_STOP#
15 PWRDWN#
11-0126
1
www.pericom.com
P-0.1
10/12/2011