PI6C10810 Datasheet, PDF (1/10 Pages) Pericom Semiconductor Corporation – 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer

PI6C10810
1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer
Features
• High-speed, low-noise, non-inverting split 1-10 buffer
• Maximum Frequency up to 250 MHz
• Low output skew < 60ps (Bank A, 2.5V)
• Low duty cycle distortion < 200ps
• Low propagation delay < 2.0ns (2.5V)
• Choice of 1.2V, 1.5V, 1.8V or 2.5V supply voltage on Bank A,
Bank B, Bank C
• Industrial temperature range: –40°C to 85°C
• Packages (Pb-free & Green): 20-pin, TSSOP (L20)
20-pin, SSOP (H20)
20-pin, QSOP (Q20)
Description
The PI6C10810 is a 1.2V to 2.5V high-speed, low-noise
1-10 non-inverting clock buffer. The key goal in designing the
PI6C10810is to target networking applications that require low-
skew, low-jitter, and high-frequency clock distribution.
Providing output-to-output skew as low as 60ps, the PI6C10810
is an ideal clock distribution device for synchronous systems.
Designing synchronous networking systems requires a tight level
of skew from a large number of outputs.
CLK0-4 operate from V_DDA supply.
CLK5-6 operate from V_DDC supply.
CLK7-9 operate from V_DDB supply.
Block Diagram
BUF_IN
V_DDA
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
Pin Configuration
BUF_IN ₁
GND ₂
CLK0 ₃
VDDA ₄
CLK1 ₅
GND ₆
CLK2 ₇
VDDA ₈
CLK3 ₉
GND ₁₀
20 VDDB
19 ^CLK9
18 CLK8
17 GND
16 ^CLK7
15 VDDC
14 CLK6
13 GND
12 CLK5
11 CLK4
CLK6
11-0015
CLK7
CLK8
CLK9
V_DDC V_DDB
Pin Description
Pin Name
BUF_IN
CLK [0:9]
GND
V_DDA, V_DDB, V_DDC
Description
Input
Outputs
Ground
Power (1.2V, 1.5V, 1.8V, 2.5V)
1
PS9014A
02/23/11