PI4ULS3V08M Datasheet, PDF (1/8 Pages) Pericom Semiconductor Corporation – 1.2V to 3.6V Universal Bi-directional Level Shifter with Automatic Direction Control & Advanced Package Solution

PI4ULS3V08M
1.2V to 3.6V Universal Bi-directional Level Shifter with Automatic
Direction Control & Advanced Package Solution
Features
• PI4ULS3V08M is designed for low voltage operation:
1.2V to 3.6V
• Universal bidirectional level shifting with automatic direction
control
• Fast bus speeds up to 160 Mbps
• I_OFF supports partial Power-Down mode operation
• Drive Capability 12mA
• Independent translation of each bit
• Each supply rail is configurable over supply range
• ESD Protection exceeds JESD22
– 2000V Human Body Model (A114-B)
– 200V Machine Model (A115-A)
• Latch-up performance exceeds 100mA per JESD 78
• Industrial operation at –40°C to +85°C
• Packaging (Pb-free & Green):
– 32-contact TQFN (ZL)
Applications
• Voltage Translation
• Bus Relay
• Mobile Devices
Description
PI4ULS3V08M, is a 8-bit (octal) non-inverting bus
transceiver with two separate supply rails: A port (V_CCA)
and B port (V_CCB) are set to operate at 1.2V to 3.6V. This
arrangement permits universal bidirectional translation of
differential signal levels over the voltage ranges.
The PI4ULS3V08M is designed for asynchronous communication
between data buses. Data is transmitted from the A bus to the B
bus, or vice versa, without direction control. All A_X, and B_X are
tri-stated when data is coming from both directions at the same
time. The output-enable (OE) input is used to disable outputs so
buses are isolated.
The control pins, OEx, TEST_EN and OUT_SEL are supplied by
V_CCB.
The device is fully specified for partial-power-down applications
using I_OFF. The I_OFF circuitry disables the outputs, preventing
damaging current backflow through the device when it is powered
down.
To ensure the high impedance state during power-up or power-
down, the output-enable (OEx) input should be tied to V_CC through
a pullup resistor: the minimum value of the resistor is determined
by the current-sinking capability of the driver.
Pin Configuration
Block Diagram
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B1
1
B2
2
VCCB
3
B3
4
B4
5
GND
6
B5
7
B6
8
VCCB
9
B7
10
B8
11
27
A1
26
A2
25
VCCA
24
A3
23
A4
22
GND
21
A5
20
A6
19
VCCA
18
A7
17
A8
06-0046
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1
PS8774F
04/05/06