PI2EQX4432D Datasheet, PDF (1/6 Pages) Pericom Semiconductor Corporation – 2.5 Gbps x2 Lane PCI Express Repeater/Equalizer with Signal Detect and Flow-Through Pinout

PI2EQX4432D
2.5 Gbps x2 Lane PCI Express Repeater/Equalizer
with Signal Detect and Flow-Through Pinout
Features
• Two High Speed PCI Express lanes
• Supports PCI Express data rates (2.5 Gbps) on each lane
• Adjustable Receiver Equalization
• Input Signal Level Detect & Output Squelch on all Channels
• Output De-emphasis = -3.5dB
• 100–Ohm Differential CML I/O’s
• Low Power (100mW per Channel)
• Standby Mode – Power Down State
• V_DD Operating Range: 1.8V +/-0.1V
• Packaging (Pb-free & Green): 48-contact TQFN
Description
Pericom Semiconductor’s PI2EQX4432D is a low power,
PCI Express compliant signal Re-Driver. The device provides
programmable equalization, to optimize performance by reducing
Inter-Symbol Interference (ISI). PI2EQX4432D supports two
100−Ohm Differential CML data I/O’s between the Protocol
ASIC to a switch fabric, across a backplane, or extends the signals
across other distant data pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the Re-Driver.
Whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the PCI Express signal after the Re-
Driver.
A low-level input signal detection and output squelch function
is provided for all four channels. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channels input signal level (on xl+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the output driver
switches off, and the pin is pulled to VDD via a high impedance
resistor.
In addition to providing serial re-conditioning, Pericom's
PIEQX4432D also provides a power management Stand-by mode
operated by the enable pins.
Block Diagram
Signal Detect
Pin Description (Top View)
xl+
xl–
SEL–EQ_x
Equalizer
Limiting
Amp
CML
xO+
xO–
SEL–OL_x SEL–DE_x
EN_X
Power
Management
CLK+
CLK–
07-0106
– – Repeat 4 Times – –
Clock Buffer
EN_CLK
IREF
CLKO+
CLKO–
1
AI+
AI–
VDD
BO+
BO–
VDD
CI+
CI–
VDD
DO+
DO–
VDD
48 47 46 45 4443 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
GND
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 1718 19 20 21 22 23 24
AO+
AO–
VDD
BI+
BI–
VDD
CO+
CO–
VDD
DI+
DI–
GND
PS8888A
04/26/07