P174FCT2273T Datasheet, PDF (1/4 Pages) Pericom Semiconductor Corporation – Fast CMOS Octal D Flip-Flop with Master Reset

PI74FCT273T
(25Ω Series) P174FCT2273T
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Fast CMOS Octal D Flip-Flop
with Master Reset
Product Features
Product Description
• PI74FCT273/2273T is pin compatible with bipolar FAST™
Series at a higher speed and lower power consumption
• 25Ω series resistor on all outputs (FCT2XXX only)
• TTL input and output levels
• Low ground bounce outputs
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 20-pin 173 mil wide plastic TSSOP (L)
– 20-pin 300 mil wide plastic DIP (P)
– 20-pin 150 mil wide plastic QSOP (Q)
– 20-pin 150 mil wide plastic TQSOP (R)
– 20-pin 300 mil wide plastic SOIC (S)
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6/0.8 micron CMOS
technology, achieving industry leading speed grades. All
PI74FCT2XXX devices have a built-in 25-ohm series resistor on
all outputs to reduce noise because of reflections, thus eliminating
the need for an external terminating resistor.
The PI74FCT273T and PI74FCT2273T is an 8-bit wide octal
designed with eight edge-triggered D-type flip-flops with individual
D inputs and O outputs. The common buffered Clock (CP) and
Master Reset (MR) load and resets (clear) all flip-flops
simultaneously. The register is fully edge-triggered. The D input
state, one setup time before the LOW-to-HIGH clock transition, is
transferred to the corresponding flip-flop's O output. All outputs
will be forced LOW independently of Clock or Data inputs by a
LOW voltage level on the MR input.
Device models available upon request.
Logic Block Diagram
D0
D1
D2
D3
D4
D5
D6
D7
CP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
MR
O0
O1
O2
O3
O4
O5
O6
O7
Product Pin Configuration
MR 1
20 Vcc
O0 2
19 O7
D0
D1
O1
O2
D2
D3
O3
3 _20-PIN 18
4 _L20 17
5 _P20 16
6 _Q20 15
7 _R20 14
8 _S20 13
9
12
D7
D6
O6
O5
D5
D4
O4
GND 10
11 CP
Product Pin Description
Pin Name
MR
CP
D0-D7
O0-O7
GND
VCC
Description
Master Reset (Active LOW)
Clock Pulse Input
(Active Rising Edge)
Data Inputs
Data Outputs
Ground
Power
Truth Table⁽¹⁾
Inputs
Outputs
Mode
MR CP DN ON
Reset (Clear) L X X L
Load "1"
H
↑h H
Load "0"
H
↑
l
L
1. H = High Voltage Level
h = High Voltage Level one setup time
prior to the LOW-to-HIGH Clock
transition
L = Low Voltage Level
l = LOW Voltage Level one setup time
prior to the LOW-to-HIGH Clock
Transition
X = Don’t Care
↑ = LOW-to-HIGH Clock Transition
1
PS2013A 03/09/96