PE83512 Datasheet, PDF (2/6 Pages) Peregrine Semiconductor Corp. – DC - 1500 MHz Low Power CMOS Divide-by-4 Prescaler

Figure 3. Pin Configuration
V_DD
1
IN
2
N/C
3
GND 4
8 _GND
PE83512
7 _OUT
6 _CTL
5 OUTB
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
Pin
Name
V_DD
4_I.7_N5
N/C
GND
OUTB
CTL
OUT
GND
Description
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
No connection. This pin should be left
open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Inverted divided frequency output. This pin
should be coupled with a capacitor
(eg 1000 pF).
Control pin. When grounded OUTB is
enabled.
Divided frequency output pin. This pin
should be coupled with a capacitor
(eg 1000 pF).
Ground Pin.
Table 3. Absolute Maximum Ratings
Symbol
VDD
Pin
V_IN
Parameter/Conditions
Supply voltage
Input Power
Voltage on input
T_ST
T_OP
VESD
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model, MIL-STD 883)
Min Max Units
4.0
15
-0.3 VDD
+0.3
-65 150
-55 125
V
dBm
V
°C
°C
2000 V
PE83512
Product Specification
Electrostatic Discharge (ESD) Precautions
When handling this UTSi^ device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi^ CMOS
devices are immune to latch-up.
Device Functional Considerations
The PE83512 divides an input signal, up to a
frequency of 1500 MHz, by a factor of four
thereby producing an output frequency at one
fourth the input frequency. To work properly at
higher frequency, the input and output signals
(pins 2 , 7 & optional 5) must be AC coupled via
an external capacitor, as shown in the test circuit
in Figure 4. The input may be DC coupled for
low frequency operation with care taken to remain
within the specified DC input range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 7 for a layout example.
OUTB Control
Pin 6 controls weather OUTB is enabled or
disabled. Pin 6 has an internal pull-up resistor.
With no connection (floating), OUTB is disabled.
By grounding pin 6, OUTB is enabled. By
enabling OUTB, this part will use roughly 5 mA
more current.
Copyright  Peregrine Semiconductor Corp. 2003
Page 2 of 6
File No. 70/0117~02A| UTSi  CMOS RFIC SOLUTIONS