PE83511_06 Datasheet, PDF (2/7 Pages) Peregrine Semiconductor Corp. – DC - 1500 MHz Low Power UltraCMOS Divide-by-2 Prescaler Military Operating Temperature Range

Figure 3. Pin Configuration (Top View)
VDD
1
IN
2
N/C
3
GND 4
88 _GND
PE83511
7 _OUT
6 CTL
5 OUT
Table 2. Pin Descriptions
Pin
Pin
No. Name
Description
1
VDD
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
2
IN
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
3
N/C No connection. This pin should be left open.
Ground pin. Ground pattern on the board
4
GND should be as wide as possible to reduce
ground impedance.
Inverted divided frequency output. This pin
5
OUTB should be coupled with a capacitor
(eg 1000 pF).
6
CTL
Control pin. When grounded OUTB is
enabled.
7
OUT
Divided frequency output. This pin should
be coupled with a capacitor (eg 1000 pF).
8
GND Ground Pin.
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Pin
VIN
TST
TOP
VESD
Supply voltage
Input Power
Voltage on input
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model, MIL-STD 883)
4.0
V
15 dBm
-0.3
VDD
+0.3
V
-65 150 °C
-55 125 °C
2000 V
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
PE83511
Product Specification
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Device Functional Considerations
The PE83511 divides an input signal, up to a
frequency of 1500 MHz, by a factor of two thereby
producing an output frequency at half the input
frequency. To work properly at higher frequency,
the input and output signals (pins 2, 7 & optional
5) must be AC coupled via an external capacitor.
The input may be DC coupled for low frequency
operation with care taken to remain within the
specified DC input range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 8 for a layout example.
OUTB Control
Pin 6 controls whether OUTB is enabled or
disabled. Pin 6 has an internal pull-up resistor.
With no connection (floating), OUTB is disabled.
By grounding pin 6, OUTB is enabled. By
enabling OUTB, this part will consume roughly
5 mA more current.
Document No. 70-0113-03 │ UltraCMOS™ RFIC Solutions