PE83501 Datasheet, PDF (2/7 Pages) Peregrine Semiconductor Corp. – 3.5 GHz Low Power CMOS Divide-by-2 Prescaler

Figure 3. Pin Configuration
VDD ¹
F_in
2
DEC 3
GND 4
8 _GND
PE83501
7
F_out
6 _GND
5 GND
Table 2. Pin Descriptions
Pin
Pin
No. Name
Description
1
VDD Power supply pin. Bypassing is required.
2
F_in
Input signal pin. DC blocking capacitor
required (15 pF typical)
3
DEC Power supply decoupling pin. Place a
capacitor as close as possible and connect
directly to the ground plane.
4
GND Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
5
GND Ground pin.
6
GND Ground pin.
7
F_out Divided frequency output pin. DC blocking
capacitor required (47 pF typical)
8
GND Ground pin.
Table 3. Absolute Maximum Ratings
Symbol
VDD
Pin
T_ST
T_OP
VESD
Parameter/Conditions Min Max Units
Supply voltage
Input Power
Storage temperature
range
Operating temperature
range
ESD voltage (Human
Body Model)
4.0
V
15 dBm
-65 150 °C
-55 125 °C
250
V
PE83501
Product Specification
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Device Functional Considerations
The PE83501 divides a 400 MHz to 3.5 GHz input
signal by two, producing a 200 MHz to 1.75 GHz
output signal. To work properly, pin 3 must be
supplied with a bypass capacitor to ground. In
addition, the input and output signals (pins 2 & 7)
must be AC coupled via an external capacitor, as
shown in the test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 11 for a layout example.
Copyright  Peregrine Semiconductor Corp. 2003
Page 2 of 7
File No. 70/0124~00B | UTSi  CMOS RFIC SOLUTIONS