PE4231 Datasheet, PDF (2/7 Pages) Peregrine Semiconductor Corp. – SPDT High Power UltraCMOS - DC 1.3 GHz RF Switch

Figure 3. Pin Configuration (Top View)
V_DD ¹
CTRL ²
GND ³
RFCommon ⁴
4231
8 _RF1
7 _GND
6 _GND
5 _RF2
Table 2. Pin Descriptions
Pin
No.
Pin Name
Description
1
V_DD
Nominal +3 V supply connection.
2
CTRL
CMOS or TTL logic level:
High = RFCommon to RF1 signal path
Low = RFCommon to RF2 signal path
3
GND
Ground connection. Traces should be
physically short and connected to ground
4
RF Common Common RF port for switch.¹
5
RF2
RF2 port.¹
6
GND
Ground Connection. Traces should be
physically short and connected to ground
7
GND
Ground Connection. Traces should be
physically short and connected to ground
8
RF1
RF1 port.¹
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 V_DC.
Table 3. Absolute Maximum Ratings
Symbol
V_DD
V_I
V_CTRL
T_ST
T_OP
PIN
V_ESD
Parameter/
Conditions
Power supply voltage
Voltage on any input ex-
cept for the CTRL input
Voltage on CTRL input
Storage temperature
range
Operating temperature
range
Input power (50Ω)
ESD voltage (Human
Body Model)
Min Max
-0.3 4.0
-0.3
V_DD+
0.3
5.0
-65 150
-40 85
33
200
Units
V
V
V
°C
°C
dBm
V
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
PE4231
Product Specification
Table 4. DC Electrical Specifications
Parameter
Min Typ Max
V_DD Power Supply
Voltage
2.7
3.0
3.3
I_DD Power Supply Current
(V_DD = 3V, V_CNTL = 3V)
29
35
Control Voltage High
0.7xV_DD
Units
V
µA
V
Control Voltage Low
0.3xV_DD
V
Table 5. Truth Table
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFCommon to RF1
RFCommon to RF2
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V_DD. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V_DD pin when the
control logic input voltage level exceeds V_DD.)
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Document No. 70-0097-01 │ UltraCMOS™ RFIC Solutions