PE3501 Datasheet, PDF (2/8 Pages) Peregrine Semiconductor Corp. – 3500 MHz Low Power UltraCMOS™ Divide-by-2 Prescaler

Figure 3. Pin Configuration (Top View)
VDD
1
FIN
2
DEC 3
GND 4
3501
8 GND
7
FOUT
6 NC
5 GND
Table 2. Pin Descriptions
Pin
Pin
No. Name
Description
1
VDD Power supply pin. Bypassing is required.
2
Fin
Input signal pin. DC blocking capacitor
required (15 pF typical)
Power supply decoupling pin. Place a ca-
3
DEC pacitor as close as possible and connect
directly to the ground plane.
Ground pin. Ground pattern on the board
4
GND should be as wide as possible to reduce
ground impedance.
5
GND Ground pin.
6
NC
No Connection. This pin should be left
open.
7
Fout
Divided frequency output pin. DC blocking
capacitor required (47 pF typical)
8
GND Ground pin.
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Supply voltage
4.0
V
Pin
Input Power
15 dBm
TST
Storage temperature range -65 150 °C
TOP
Operating temperature
range
-40 85
°C
VESD
ESD voltage (Human Body
Model)
250
V
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
PE3501
Product Specification
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Device Functional Considerations
The PE3501 divides a 400 MHz to 3500 MHz
input signal by two, producing a 200 MHz to 1750
MHz output signal. To work properly, pin 3 must
be supplied with a bypass capacitor to ground. In
addition, the input and output signals (pins 2 & 7)
must be AC coupled via an external capacitor, as
shown in the test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 11 for a layout example.
©2005 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0111-03 │ UltraCMOS™ RFIC Solutions