PE9701 Datasheet, PDF(11/13 Page) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications

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PE9701 Datasheet, PDF (11/13 Pages) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications

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PE9701

Product Specification

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active âhighâ.

Table 9. Enhancement Register Bit Functionality

Bit Function

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Reserved**

Power down

Counter load

MSEL output

Prescaler output

fp, fc OE

Power down of all functions except programming interface.

Immediate and continuous load of counter programming as directed by the Bmode and

Smode inputs.

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Drives the raw internal prescaler output (fmain) onto the Dout output.

fp, fc outputs disabled.

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

from the main Counter (fp) and the reference

counter (fc). It has two outputs, namely PD_U,

and PD_D. If the divided VCO leads the divided

reference in phase or frequency (fp leads fc),

PD_D pulses âhighâ. If the divided reference leads

the divided VCO in phase or frequency (fr leads

fp), PD_U pulses âhighâ. The width of either pulse

is directly proportional to phase offset between the

two input signals, fp and fc.

The signals from the phase detector couple

directly to a charge pump. PD_U controls a

current source at pin CP with constant amplitude

and pulse duration approximately the same as

PD_U. PD_D similarly drives a current sink at

pin CP. The current pulses from pin CP are low

pass filtered externally and then connected to the

VCO tune voltage. PD_U pulses result in a

current source, which increases the VCO

frequency; PD_D pulses result in a current sink,

which decreases VCO frequency.

A lock detect output, LD is also provided, via the

pin Cext. Cext is the logical âNANDâ of PD_U and

PD_D waveforms, which is driven through a series

2k â¦ resistor. Connecting Cext to an external

shunt capacitor provides integration. Cext also

drives the input of an internal inverting comparator

with an open drain output. Thus LD is an âANDâ

function of PD_U and PD_D. See Figure 4 for a

schematic of this circuit.

Document No. 70-0035-02 â www.psemi.com

Page 11 of 13

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