PE64101 Datasheet, PDF (10/13 Pages) Peregrine Semiconductor Corp. – UltraCMOS® Digitally Tunable Capacitor (DTC) 100 - 3000 MHz

PE64101
Product Specification
Evaluation Board
The 101-0700 Evaluation Board (EVB) was
designed for accurate measurement of the DTC
impedance and loss. Two configurations are
available: 1 Port Shunt (J3) and 2 Port Shunt (J4,
J5). Three calibration standards are provided. The
open (J2) and short (J1) standards (104 ps delay)
are used for performing port extensions and
accounting for electrical length and transmission
line loss. The Thru (J9, J10) standard can be used
to estimate PCB transmission line losses for scalar
de-embedding of the 2 Port Shunt configuration (J4,
J5).
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B (ε_r = 3.48) and 2
inner layers of FR4 (ε_r = 4.80). The total thickness
of this board is 62 mils (1.57 mm). The inner layers
provide a ground plane for the transmission lines.
Each transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using
a trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.036 mm).
Figure 17. Evaluation Board Layout
101-0700
©2012 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0378-01 │ UltraCMOS^® RFIC Solutions