DAC3154 Datasheet, PDF (6/46 Pages) Pan Jit International Inc. – Dual 12-/10-Bit 500 MSPS Digital-to-Analog Converters

DAC3154
DAC3164
SLAS960 – MAY 2013
PINOUT – DAC3164
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DACCLKP 1
48 TXENABLE
DACCLKN 2
47 ALARM
CLKVDD18 3
46 SDO
ALIGNP 4
45 IOVDD
ALIGNN 5
44 SDIO
SYNCP 6
43 SCLK
SYNCN 7
42 SDENB
VFUSE 8
(MSB) D11P 9
DAC3164
41 RESETB
40 NC
D11N 10
39 NC
D10P 11
38 NC
D10N 12
37 NC
D9P 13
36 D0N
D9N 14
D8P 15
GND PAD (backside)
35 D0P (LSB)
34 D1N
D8N 16
33 D1P
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN
NAME
NO.
CONTROL/SERIAL
SCLK
43
SDENB
42
SDIO
44
SDO
46
RESETB
41
ALARM
47
TXENABLE
48
SLEEP
49
PIN ASSIGNMENT TABLE – DAC3164
I/O
DESCRIPTION
I Serial interface clock. Internal pull-down.
I Serial interface clock. Internal pull-up.
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register XYZ), the SDIO pin
in an input only. Internal Pull-down.
O Uni-directional serial interface data in 4 pin mode (register XYZ). The SDO pin is tri-stated in 3-pin
interface mode (default). Internal Pulldown.
I Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
O CMOS output for ALARM condition.
I Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.
Internal pull-down.
I Puts device in sleep, active high. Internal pull-down.
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