2N7002_07 Datasheet, PDF (2/5 Pages) Supertex, Inc – N-Channel Enhancement-Mode Vertical DMOS FETs

2N7002
ELECTRICAL CHARACTERISTICS
Static
Parameter
S ym b o l
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Drain-Source On-State Resistance
Drain-Source On-State Resistance
Zero Gate Voltage Drain Current
Gate Body Leakage
Forward Transconductance
Dynamic
B V _DSS
V _GS(th)
R
D S (o n)
R_DS(on)
I_{D S S}
I_GSS
g _fS
To ta l Ga te C ha rg e
Q_g
Gate-Source Charge
Q_gs
Gate-Drain Charge
Q
gd
Turn-On D e la y Ti me
t_on
Turn-Off D e la y Ti me
t_off
Input C apaci tance
C _iss
Output Capacitance
C _oss
Re ve rs e Tra ns fe r C a p a c i ta nc e
C _rss
Source-Drain Diode
Max. Diode Forward Current
I_s
Diode Forward Voltage
V _SD
Te s t C o nd i ti o n
V _GS=0V, I_D=10uA
V _DS=V _GS, I_D=2 5 0 uA
V =4.5V, I =75mA
GS
D
V_GS=10V, I _D=500mA
V_DS=60V, V_GS=0V
V_GS=+20V, V_DS=0V
V _DS=15V, I_D=250mA
V _DS=15V, I_D=500mA
V =4.5V
DD
V_DD=10V , R_L=20Ω
I_D=500mA , V_GEN=10V
R_G=10Ω
V_DS=25V, V_GS=0V
f=1.0MH_Z
-
I_S=250mA , V _GS=0V
Mi n.
Typ .
Max.
Uni ts
60
-
-
V
1
-
2.5
V
-
-
7.5
Ω
-
-
5
-
-
1
uA
-
-
+100
nA
200
-
-
mS
-
0.6
0.7
-
0.1
-
nC
-
0.08
-
-
9
15
ns
-
21
26
-
-
50
-
-
25
pF
-
-
5
-
-
250
mA
-
0.93
1.2
V
Switching
VDD
Test Circuit
VIN
RL
Gate Charge
VDD
Test Circuit
VGS
RL
VOUT
RG
1mA
RG
STAD-JUL.26.2007
PAGE . 2