PJSMS05C_09 Datasheet, PDF (1/4 Pages) Pan Jit International Inc. – PENTA TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION

PJSMS05C SERIES
PENTA TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 5 TVS/Zener Array family have been designed to Protect Sensitive
Equipment against ESD and to prevent Latch-Up events in CMOS circuitry
operating at 5V, 12V, 15V and 24V. This TVS array offers an integrated
solution to protect up to 5 data lines where the board space is a premium.
SPECIFICATION FEATURES
350W Power Dissipation (8/20µs Waveform)
Low Leakage Current, Maximum of 5µA at rated voltage
Very Low Clamping Voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Industry Standard Surface Mount Package SOT23-6L
100% Tin Matte Finish (RoHS Compliant)
1
654
APPLICATIONS
Personal Digital Assistant (PDA)
SIM Card Port Protection (Mobile Phone)
Portable Instrumentation
Mobile Phones and Accessories
Memory Card Port Protection
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P _pp
V _ESD
TJ
T_stg
1 23
SOT23-6L
Device Marking Code
PJSMS05C
MD5
PJSMS12C
MA2
PJSMS15C
MA5
PJSMS24C
MB4
Value
350
>25
-50 to +125
-50 to +150
Units
W
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJSMS05C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V_WRM
V_BR
I_R
V_c
V_c
Cj
Cj
Conditions
Min Typical Max
5
I _BR = 1mA
6
V_R = 5V
5
I _pp = 5A
9.5
I _pp = 24A
13
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2
200
5 Vdc Bias f = 1MHz
Between I/O pins and pin 2
110
Units
V
V
µA
V
V
pF
pF
1/13/2009
Page 1
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