PJSMF03LC Datasheet, PDF (1/5 Pages) Pan Jit International Inc. – 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION

PJSMF03LC Series
5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 5-TVS/Zener Array has been designed to Protect Sensitive Equipment against
ESD and to prevent Latch-Up events in CMOS circuitry, operating at 3.3V and 5V, as
well available for 12V, 15V, and 24V Systems. This TVS array offers an integrated
solution to protect up to 5 data lines where the board space is a premium.
SPECIFICATION FEATURES
100W Power Dissipation (8/20µs Waveform)
Low Leakage Current
Very Low Clamping Voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Operating voltage options for 3.3V, 5V, 12V, 15V, and 24V
Industry Standard SOT363 (SC70-6L) Package
1
6
5
4
APPLICATIONS
Personal Digital Assistant (PDA)
SIM Card Port Protection (Mobile Phone)
Portable Instrumentation
Mobile Phones and Accessories
Memory Card Port Protection
1
2
3
SOT363
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P _pp
V _ESD
TJ
T_stg
Value
100
25
-55 to +150
-55 to + 150
Units
W
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJSMF03LC
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (820µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V_WRM
V_BR
I_R
V_c
V_c
Cj
Cj
Conditions
Min Typical Max
3.3
I _BR = 10 mA
4.7
5.6
V_R = 3.3V
250
I _pp = 5A
7.5
I _pp = 9A
9
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2
160
3.3 Vdc Bias f = 1MHz
Between I/O pins and pin 2
90
Units
V
V
µA
V
V
pF
pF
9/14/2005
Page 1
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