PJSMDA05-6_09 Datasheet, PDF (1/4 Pages) Pan Jit International Inc. – HEX TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION

PJSMDA05-6 SERIES
HEX TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 6 TVS/Zener Array family have been designed to Protect Sensitive
Equipment against ESD and to prevent Latch-Up events in CMOS circuitry
operating at 5V, 12V, 15V and 24V. This TVS array offers an integrated
solution to protect up to 6 data lines where the board space is a premium.
SPECIFICATION FEATURES
350W Power Dissipation (8x20µsec Waveform)
Low Leakage Current, Maximum of 5µA at rated voltage
Very Low Clamping Voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Packaged in the Industry Standard SOIC-8
1
2
3
4
SOIC-8
8
7 GND
6 GND
5
APPLICATIONS
RS-232C or RS-422 Communication ports
GPIB/IEEE 485 Ports
Portable Instrumentation
5
8
4
1
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8x20µsec Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P _pp
V _ESD
TJ
T_stg
Value
350
>25
-50 to +125
-50 to +150
Units
W
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJSMDA05-6
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µsec)
Clamping Voltage (8x20µsec)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V_WRM
V_BR
I_R
V_cl
V_cl
Cj
Cj
Conditions
Min
I _BR = 1mA
6
V_R = 5V
I _pp = 5A
I _pp = 24A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 6, 7
5 Vdc Bias f = 1MHz
Between I/O pins and pin 6, 7
Typical
Max
5
5
9.8
13
225
125
Units
V
V
µA
V
V
pF
pF
7/1/2009
Page 1
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