PJSDA6V1W5 Datasheet, PDF (1/3 Pages) Pan Jit International Inc. – QUAD TVS/ZENER FOR ESD AND LATCH-UP PROTECTION

PJSDA6V1W5
QUAD TVS/ZENER FOR ESD AND LATCH-UP PROTECTION
This Quad TVS/Zener Array has been designed to Protect Sensitive Equipment
against ESD and to prevent Latch-Up events in CMOS circuitry
operating at 5Vdc and below. This TVS array offers an integrated solution to
protect up to 4 data lines where the board space is a premium.
SPECIFICATION FEATURES
150W Power Dissipation (8/20µs Waveform)
4
6
Very Low Leakage Current, Maximum of 5µA @ 5Vdc
Very low Clamping voltage (Max of 10V @ 14A 8/20µs)
IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance
Industry standard SOT353 (Also known as SC70-5L)
1
APPLICATIONS
2
3
2
1
6
Personal Digital Assistant (PDA)
SIM Card Port Protection (Mobile Phone)
Portable Instrumentation
Mobile Phones and Accessories
Computer Data Ports
3
4
SC70-5L
MAXIMUM RATINGS
Rating
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P _pp
I _pp
V _ESD
TJ
T_stg
Value
150
14
>25
-55 to +150
-55 to +150
Units
W
A
kV
°C
°C
ELECTRICAL CHARACTERISTICS Tj = 25°C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V_WRM
V_BR
I_R
V_c
V_c
Cj
Cj
Conditions
Min Typical Max
5
I _BR =1 mA
6.2
7.2
V_R = 5V
5
I _pp = 5 Amps
8.6
I _pp = 10 Amps
9.1
0 Vdc Bias f = 1MHz
Between I/O pins and pin 7
180
5 Vdc Bias f = 1MHz
Between I/O pins and pin 7
90
Units
v
V
µA
V
V
pF
pF
10/1/2005
Page 1
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