PJSDA05C-4 Datasheet, PDF (1/3 Pages) Pan Jit International Inc. – TVS ARRAY QUAD FOR ESD PROTECTION

PJSDA05C-4
TVS ARRAY QUAD FOR ESD PROTECTION
This Penta TVS Array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up
events in CMOS circuitry operating at 5Vdc and below. This TVS array offers an integrated solution to protect up
to 4 data lines where the board space is a premium.
FEATURES
• 80W power dissipation (8/20μs waveform)
• Low leakage current,maximum of 1μA@5Vdc
• Very low clamping voltage
• IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance
• In compliance with EU RoHS 2002/95/EC directives
MECHANICAL DATA
• Case: SOT23-6L molded plastic
• Terminals:Solder plated, solderable per MIL-STD-750,Method 2026
• Weight: 0.0005 ounce, 0.0141 gram
• Marking : QCG
654
MAXIMUM RATINGS
Parameter
P eak P ulse P ower (8/20μs Waveform)
Peak Pulse C urrent (8/20μs Waveform)
ESD Voltage (HBM)
O p e r a ti ng Te m p e ra t ure Ra ng e
S t o ra g e Te m p e ra t ur e Ra ng e
12 30
123
Fig.126
Symbol
PPP
I PP
VESD
TJ
TSTG
Value
80
5.0
>25
-55 to + 150
-55 to + 150
Units
W
A
kV
o_C
o_C
ELECTRICAL CHARACTERISTICS TJ=25^oC
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Reverse Stand-Off Voltage
VRWM
-
-
-
5.0
V
Reverse Breakdown Voltage
VBR
I BR=1mA
6.2
-
8.0
V
Reverse Leakage Current
IR
VR=5V
-
-
1
μA
Clamping Voltage (8/20μs)
VC
I PP=1A
-
-
12
V
Clamping Voltage (8/20μs)
VC
I PP=4A
-
-
15
V
Off State Junction Capacitance
CJ
0Vdc Bias f=1MHz Between I/O pins and pin 2
-
15
17
pF
Off State Junction Capacitance
CJ
5Vdc Bias f=1MHz Between I/O pins and pin 2
-
7
10
pF
April 30.2010-REV.00
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