PJQMF05LC Datasheet, PDF (1/4 Pages) Pan Jit International Inc. – 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION

PJQMF05LC
5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 5-TVS/Zener Array has been designed to Protect Sensitive Equipment
against ESD and to prevent Latch-Up events in CMOS circuitry
operating at 5Vdc and below. This TVS array offers an integrated solution to
protect up to 5 data lines where the board space is a premium.
6
5
4
SPECIFICATION FEATURES
100W Power Dissipation (8x20µsec Waveform)
Low Leakage Current, Maximum of 2µA @ 5Vdc
Very Low Clamping Voltage, Max of 10V @ 9Apk 8x20µsec
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Max off state Capacitance of 90pF @ 0Vdc 1 MHz
New SMT package QFN 1.6mm x 1.6mm; Max Height of 0.75mm
Same Footprint compared to the SOT563
APPLICATIONS
Personal Digital Assistant (PDA)
SIM Card Port Protection (Mobile Phone)
Portable Instrumentation
Mobile Phones and Accessories
Memory Card Port Protection
MAXIMUM RATINGS (Per Device)
1
2
3
6
5
4
1
2
3
3
2
1
QFN 2X2
4
5
6
QFN 1.6x1.6 sq mm Package
Rating
Peak Pulse Power (8x20µsec Waveform)
Peak Pulse Current (8x20µsec Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P _pp
I _pp
V _ESD
TJ
T_stg
Value
100
10
>25
-55 to +125
-55 to + 150
Units
W
A
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8x20µsec)
Clamping Voltage (8x20µsec)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V_WRM
V_BR
I_R
V_cl
V_cl
Cj
Cj
Conditions
Min Typical Max
5
I _BR = 1 mA
6
7.2
V_R = 5V
2.0
I _pp = 5A
9
I _pp = 9A
10
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2
90
5 Vdc Bias f = 1MHz
Between I/O pins and pin 2
45
Units
V
V
µA
V
V
pF
pF
1/26/2004
Page 1
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