PJQA5V6C Datasheet, PDF (1/2 Pages) Pan Jit International Inc. – 5 - TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION

PJQA5V6C
5 - TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This Quad TVS/Zener Array family have been designed to Protect Sensitive
Equipment against ESD and to prevent Latch-Up events in CMOS circuitry
operating in the 5V. This TVS array offers an integrated solution to protect up
to 5 data lines where the board space is a premium.
SPECIFICATION FEATURES
150W (8/20µs), 24W (10/1000µs) Power Dissipation
Low Leakage Current, Maximum of 2µA at rated voltage
Very Low Clamping Voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Industry Standard Surface Mount Package SOT23-6L
100% Tin Matte Finish (RoHS Compliant)
1
6
5
4
APPLICATIONS
Personal Digital Assistant (PDA)
SIM Card Port Protection (Mobile Phone)
Portable Instrumentation
Mobile Phones and Accessories
Memory Card Port Protection
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
1
2
3
SOT23-6L
Marking Code: "Q5A"
Symbol
P _pp
V _ESD
TJ
T_stg
Value
150
25
-55 to +150
-55 to +150
Units
W
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJQA5V6C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V_WRM
V_BR
I_R
V_c
V_c
Cj
Cj
Conditions
Min
I _BR =1 mA
5.3
V_R = 3.0V
I _pp = 5 Amps
I _pp = 10 Amps
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2,5
3 Vdc Bias f = 1MHz
Between I/O pins and pin 2,5
Typical Max
3.0
5.6 5.88
2
7.5
9.1
265
170
Units
V
V
µA
V
V
pF
pF
7/6/2006
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