PJESD5V6LCQ5G Datasheet, PDF (1/4 Pages) Pan Jit International Inc. – 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION

PJESD5V6LCQ5G Series
5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 5-TVS array has been designed to Protect Sensitive Equipment against ESD
and to prevent Latch-Up events in CMOS circuitry, operating at 3.3V and 5V Systems.
This TVS array offers an integrated solution to protect up to 5 data lines where the
board space is a premium.
6
5
4
SPECIFICATION FEATURES
15W Power Dissipation (8/20µs Waveform)
Low Leakage Current, Maximum of 0.5µA @ V_WRM
Very low Off-State Capacitance, Maximum of 10pF at 1MHz 0Vdc
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
100% Tin plated finish (LEAD FREE) RoHS Compliant
New SMT package QFN 1.6mm x 1.6mm; Max Height of 0.75mm
Same Footprint compared to the SOT563
APPLICATIONS
Personal Digital Assistant (PDA)
MP3 Players
Portable Global positioning Systems Port
Mobile Phones and Accessories
Memory Card Port Protection
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P _pp
V _ESD
TJ
T_stg
1
2
3
6
5
4
1
2
3
3
2
1
QFN 2X2
4
5
6
QFN 1.6x1.6 sq mm Package
Value
15
>25
-55 to +150
-55 to +150
Units
W
kV
°C
°V
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJESD5V6LCQ5G
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V_WRM
V_BR
I_R
V_c
V_c
Cj
Cj
Conditions
Min Typical Max
3.3
I _BR =1mA
V_R = 3.3V
5.3 5.6 5.88
0.5
I _pp = 1 A
7.0
I _pp = 2 A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2
3.3 Vdc Bias f = 1MHz
Between I/O pins and pin 2
8.0
9.6
10
6.2
8
Units
V
V
µA
V
V
pF
pF
10/5/2006
Page 1
www.panjit.com