PJESD5V0QL4G Datasheet, PDF (1/3 Pages) Pan Jit International Inc. – LOW CAPACITANCE TVS/ZENER ARRAYS FOR ESD PROTECTION

PJESD5V0QL4G, L5G
LOW CAPACITANCE TVS/ZENER ARRAYS FOR ESD PROTECTION
These 4 and 5 TVS/Zener Arrays have been designed to protect sensitive equipment
against ESD in CMOS circuitry operating at 5V. These TVS arrays offers an
integrated solution to protect 4 or 5 data lines in applications, where the board
space is a premium, in a Quad Flat no-Lead package that only occupies an area of
1.8 sq mm.
SPECIFICATION FEATURES
IEC61000-4-2 ESD 20kV Air, 15kV Contact Compliance
Low Leakage Current, Maximum of 1µA at rated voltage
Maximum Capacitance of 15pF per device at 0Vdc 1MHz
Peak Power Dissipation of 20W under 8/20µs Waveform
Quad Flat No Lead package QFN (1.2x1.5 sq mm, Height: 0.75mm)
Lead Free Package 100% Tin Plating, Matte finish
APPLICATIONS
Personal Digital Assistant (PDA)
Digital Cameras
Portable Instrumentation
Mobile Phones and Accessories
MP3 Players
1
PJESD5V0QL4G
GND
1
23
6
54
NC
PJESD5V0QL5G
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
ESD Voltage (HBM Per MIL STD883C - Method 3015-6)
Operating Temperature Range
Storage Temperature Range
Symbol
P _PP
I _PPM
V _ESD
TJ
T_stg
Value
20
TBD
20
-55 to +150
-55 to +150
Units
W
A
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Symbol
V _WRM
V_BR
I_R
V_c
Cj
Conditions
I _BR =1mA
V_R = 5V
I _pp = TBD
0 Vdc Bias f = 1MHz
betweeen I/O lines and
Min Typical Max
5
6
1
TBD TBD
TBD 15
Units
V
V
µA
V
pF
7/18/2006
Page 1
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