PJDLLLC05 Datasheet, PDF (1/3 Pages) Pan Jit International Inc. – Low Capacitance TVS Diode Array

PJDLLLC05
Low Capacitance TVS Diode Array
This diode array is configured to protect up to two high speed data
transmission lines, used in Low Voltage Differential Signal (LVDS) ports.
Acting as a line terminator, minimizes overshoot and undershoot conditions
due to bus impedance, as well as protect against over-voltage events as
electrostatic discharges. The line-line concept minimizes the problems to
customers to re-route PCB lines, simplifying the design.
SPECIFICATION FEATURES
Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground
Maximum Leakage Current of 1.0µA @ VRWM
Industry Standard SMT Package SOT563
IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact*
100% Tin Matte finish (LEAD-FREE PRODUCT)
APPLICATIONS
USB 2.0 and Firewire Port Protection
HDMI Version 1.3
DVI
MARKING : 05
SOT563 Package
1
2
3
6
5
4
Line1 Gnd Line2
6
5
4
1
2
3
Line1 Gnd Line2
Note: pins 1and 6 (Line1), pins 3 and 4 (
Line2) and pins 2 and 5 (Gnd) must be
connected externally, as the drawing
attached below.
I/O Data line +
1
6
Ground
2
5
I/O Data line -
3
4
Line-line concept ease the PCB design, directly placing the device over
the data lines, opening only the contact points. VREF is fixed by the
operating voltage, referenced to the ground.
MAXIMUM RATINGS Tj = 25°C Unless otherwise noted
Rating
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
Operating Junction Temperature Range
Storage Temperature Range
Soldering Temperature, t max = 10s
Symbol
P_PPM
I _PP
T_J
T_stg
T_L
Value
50
6
-55 to +125
-55 to +150
260
Units
W
A
°C
°C
°C
7/23/2009
Page 1
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