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ED1002CT_05 Datasheet, PDF (1/2 Pages) Pan Jit International Inc. – SURFACE MOUNT SUPER FAST RECOVERY RECTIFIER
DATA SHEET
ED1002CT~ED1006CT
SURFACE MOUNT SUPER FAST RECOVERY RECTIFIER
VOLTAGE 200 to 600 Volts CURRENT 10 Amperes
FEATURES
• For surface mounted applications
• Low profile package
• Built-in strain relief
• Easy pick and place
• Superfast recovery times for high efficiency
• Plastic package has Underwriters Laboratory
Flammability Classification 94V-O
• Glass passivated junction
• Pb free product are available : 99% Sn above can meet Rohs environment
substance directive request
TO-251AB
.264(6.7)
.248(6.3)
.216(5.5)
.200(5.1)
MECHANICAL DATA
Case: D PAK/TO-252 molded plastic
Terminals: Solder plated, solderable per MIL-STD-202G,Method 208
Polarity: Color band denotes cathode
Standard packaging: 16mm tape (EIA-481)
Weight: 0.015 ounce, 0.4 gram.
.032(0.8)
.012(0.3)
.09 .09
(2.3) (2.3)
Unit : inch (mm)
.098(2.5)
.082(2.1)
.024(0.6)
.016(0.4)
.071(1.8)
.051(1.3)
.02(0.5)
MAXIMUM RATING AND ELECTRICAL CHARACTERISTICS
Ratings at 25°C ambient temperature unless otherwise specified. Single phase, half wave, 60 Hz, resistive or inductive load.
For capacitive load, derate current by 20%
PARAMETER
Maximum Recurrent Peak Reverse Voltage
SYMBOL ED1002CT ED1003CT ED1004CT ED1006CT UNITS
VRRM
200
300
400
600
V
Maximum RMS Voltage
VRMS
140
210
280
420
V
Maximum DC Blocking Voltage
Maximum Average Forward Current .375"(9.5mm)
lead length at Tc=100OC
Peak Forward Surge Current, 8.3ms single half sine-wave
superimposed on rated load(JEDEC method)
Maximum Forward Voltage at 5.0A
Maximum DC Reverse Current TA=25 OC
at Rated DC Blocking VoltageTA=100 OC
Maximum Reverse Recovery Time (Note 1)
Maximum thermal Resistance (Note 2)
Operating and Storage Temperature RangeTJ,TSTG
VDC
IAV
IFSM
VF
IR
TRR
RθJC
RθJA
TJ,TSTG
200
0.95
300
400
10.0
100
1.3
5.0
50
35
11
80
-55 TO +150
600
V
A
A
1.7
V
uA
ns
OC / W
OC
NOTES:
1. Reverse Recovery Test Conditions: IF=.5A, IR=1A, Irr=.25A.
2. Mounted on P.C. Board with 14mm2 (.013mm thick) copper pad areas.
3. Both Bonding and Chip structure are available.
REV.0-MAR.21.2005
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