MN3610H Datasheet, PDF (4/5 Pages) Panasonic Semiconductor – 2048-Bit High-Responsivity CCD Linear Image Sensor

CCD Linear Image Sensor
MN3610H
Note 6) The signal output pin DC level (V_OS) and the compensation output pin DC level (V_DS) are the voltage values shown in the
following figure.
OS
Reset feed
DS
through level
V_OS
V_DS
VSS
VSS
s Pin Descriptions
Pin No.
Symbol
Pin name
1
OS
Signal output
2
DS
Compensation output
3
VDD
Power supply
4
ø_R
Reset clock
5
ø _1B
CCD Final stage clock (Phase 1)
6
ø _1A
CCD Clock (Phase 1)
7
NC
Non connection
8
NC
Non connection
9
NC
Non connection
10
NC
Non connection
11
NC
Non connection
12
NC
Non connection
13
NC
Non connection
14
NC
Non connection
15
NC
Non connection
16
NC
Non connection
17
NC
Non connection
18
NC
Non connection
19
ø 2A
CCD Clock (Phase 2)
20
ø2B
CCD Final stage clock (Phase 2)
21
øSG
Shift gate clock
22
VSS
Ground
Note) Connect all NC pins externally to VSS.
Condition
s Construction of the Image Sensor
The MN3610H can be made up of the three sections of—a)
photo detector region, b) CCD transfer region (shift register),
and c) output region.
a) Photo detector region
• The photoelectric conversion device consists of an 11µm
floating photodiode and a 3µm channel stopper for each
pixel, and 2048 of these devices are linearly arranged side by
side at a pitch of 14µm.
• The photo detector's windows are 14µm × 14µm squares and
light incident on areas other than these windows is optically
shut out.
• The photo detector is provided with 52 optically shielded
pixels (black dummy pixels) which serve as the black
reference.
b) CCD Transfer region (shift register)
• The light output that has been photoelectrically converted is
transferred to the CCD transfer for each odd and even pixel at
the timing of the shift clock (øSG). The optical signal electric
charge transferred to this analog shift register is successively
transferred out and guided to the output region.
• A buried type CCD that can be driven by a two phase clock
(ø1, ø2) is used for the analog shift register.
c) Output region
• The signal charge that is transferred to the output region is
sent to the detector where impedance transformation is done
using two source follower stages.
• The DC level component and the clock noise component not
containing optical signals are output from the DS pin.
• By carrying out differential amplification of the two outputs
OS and DS externally, it is possible to obtain an output signal
with a high S/N ratio by reducing the clock noise, etc.