MN102H74D Datasheet, PDF (3/5 Pages) Panasonic Semiconductor – MN102H74D

 DMA controller
4-ch.
DMA transfer enabled between memory and memory or memory and peripheral register by set interrupt factor and software
activation setting
Transfer unit : bytes/word
Transfer mode : 1 word/burst (max. 128 K bytes)
Transfer addressing : source/destination pointer fix/increment
High-speed transfer enabled between USB-FIFO and internal RAM in single address mode
 USB Functions
Conforms to USB1.1.
USB transceiver built-in
Full-speed (12 Mbps) supported.
9 end points (FIFO built-in independently)
FIFO size
(EP0, 1, 2, 3, 4, 5, 6, 7, 8) : 64, 128, 128, 128, 128, 128, 128, 128, 128 bytes
・EP0
Control transfer
IN/OUT (two ways)
・EP1 to EP8
Interrupt/Bulk/Isochronous transfer supported.
Settable to IN or OUT.
Double Buffering function supported.
When the MAXP size is set to a half or less of the MAXFIFO size for each EP, the Double Buffering function is made valid
automatically.
 I/O Pins
I/O
77
Common use : 77 (pull-up resistance specifiable)
 A/D converter
10-bit × 8-ch. (with S/H)
 Special Ports
USB ports (D+, D-)
 Notes
4 multiply PLL built-in, generation of internal 48 MHz at external oscillation 12 MHz
 Electrical Charactreistics (Supply current)
Parameter
Symbol
Condition
Limit
Unit
min typ max
Operating supply current
Supply current at STOP
Supply current at HALT0
IDDopr
IDDS
IDDH
VI = VDD or VSS, output open
f = 12 MHz , VDD = 3.3 V
Pin with pull-up resistor is open all other input pins and
Hi-Z state input/output pins are simultaneously applied
VDD or VSS level
f = 12 MHz , VDD = 3.3 V, output open
65+10α* mA
70 µA
30+10α* mA
(Ta = –20°C to +70°C , VDD = 3.3 V, VSS = 0 V)
Note) * "α" depends on products.
MN102H74D, MN102H74G α= 0
MN102HF74G α = 1
 Development tools
In-circuit Emulator
PX-ICE102H74-LQFP100-P-1414
MAE00011GEM