MN101D09E Datasheet, PDF (2/5 Pages) Panasonic Semiconductor – MN101D09E

MN101D09E
 OSD
Display mode ........................... Menu(Internal synchronized ) display, super impose(external synchronized) display
Applicable broadcasting system....NTSC, PAL, PAL-M, PAL-N
Screen configuration ................24 characters × 2n rows (n = 1 to 6)
Character type .......................... max. 128 character types (variable, include special characters)
Character size ........................... 12 × 18 dots (Vertical direction : 1 dot for 2H at not enlargement)
Enlarged characters .................. each × 2 settings in horizontal and vertical
Character interpolation.............none
Line background color ............. 8-hue settable in the row unit at menu display
Line background intensity........8 gradations settable in the row unit
Screen background color..........8-hue settable at omenu display
Character color ......................... white
Character intensity ................... 8 gradations settable in the row unit
Frame function ......................... 1-dot frame in 4 directions
Frame intensity.........................4 gradations settable in the row unit
Blinking....................................none (covered by software)
Inverted character.....................settable in the character unit
Halftone.................................... none
Input ......................................... composite video signal input (output level : 1 V[p-p] / 2 V[p-p])
Clamp method .......................... sync tip clamp, clamp level in 4 levels
Output ...................................... composite video output
Measure against image fluctuation......built-in AFC circuit
Dot clock .................................. 1/2 of OSC oscillation clock (automatic phase adjustment)
 XDS
Built-in U.S. closed caption data slicer (optional 1 line data can be extracted.)
 I/O Pins
I/O
Input
56
Common use : 45
1
Common use : 1
 A/D converter
8-bit × 11-ch. (without S/H)
 PWM
13-bit × 2-ch. (at repetition cycle 572 ms at 14.32 MHz),
8-bit × 1-ch. (at repetition cycle 71.5 ms, 0.572 ms, 1.14 ms, 2.29 ms at 14.32 MHz)
 ICR
16-bit × 2-ch.(Speed system),
18-bit × 4-ch.(Phase system)
 OCR
16-bit × 3 (Synchronous output × 2, Rec CTL × 1 )
 Special Ports
3-state output (PTO) VLP pin; CTL input; Capstan FG input; Cylinder(Drum) PG/FG inputs; HSW output; Head amp/ Rotary control
outputs; output of 1/4 OSC oscillation clock (1 V[p-p])
 ROM Correction
Correcting address designation : up to 3 addresses possible
Correction method : correction program being saved in internal RAM
MAD00033EEM