NN30320A Datasheet, PDF (15/33 Pages) Panasonic Semiconductor – 3 A Synchronous DC-DC Step down Regulator

Doc No. TA4-EA-06187
Revision. 2
Product Standards
NN30320A
OPERATION (Continued)
6. Power ON / OFF Sequence
(1) When the EN pin is set to High after the V_IN settles,
the BGR and the VREG start up. (Recommended
V_IN rise time setting is greater than or equal to
10 µs and less than or equal to 1 s.)
(2) When the VREG pin exceeds its threshold value,
the UVLO is released and the Soft Start Sequence
is enabled.
The capacitor connected to the SS pin begins to
charge and the SS pin voltage increases linearly.
(3) The VOUT pin (DC-DC Output) voltage increases
at the same rate as the SS pin.
Normal operation begins after the VOUT pin
reaches the set voltage.
(4) When the EN pin is set to Low, the BGR, VREG
and UVLO stop operation. The VOUT pin / SS pin
Voltage starts to drop and the VOUT pin discharge
time depends on the value of the Feedback
resistors and the output load current.
Note : The SS pin capacitor should be discharged
completely before restarting the startup
sequence.
An incomplete discharge process might result
in an overshoot of the output voltage.
Greater than or equal to 10 µs, Less than or equal to 1 s
V_IN ^90%
EN
VREG
4.2 V
UVLO
SS
Soft Start Time [s] =
0.6 _{ Css}
2µ
0.6 V
VFB
VOUT
Delay
Time
[s]
=
0.09
2µ

C_SS
+
1
m
PGOOD
(1) (2) (3)
(4)
Figure : Power ON / OFF Sequence
Established : 2013-06-20
Revised : 2015-02-08
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