AN5829S Datasheet, PDF (14/17 Pages) Panasonic Semiconductor – Sound multiplex decoder IC for the U.S. televisions

AN5829S
ICs for TV
s Technical Information
[1] I²C bus (continued)
1. Receiving mode (continued)
<I²C of this IC>
1) Enhances adjustment-free mechanism of the TV set thanks to DAC control 3 and 9 switches
2) Auto-increment function
• Sub address 0 ^*: Auto-increment mode
(Data sequential transfer leads to the sequential change of sub address, so that the data is inputted.)
• Sub address 8 ^*: Data renewal mode
(With sequential data transfer, data are inputted in the same sub address.)
3) I²C bus protocol
• Slave address
• Format (normal)
S Slave address W A Sub address A Data byte A P
Start
condition
Acknowledge bit
Write Mode: 0
Stop
condition
• Auto-increment mode/data renewal mode
S Slave address W A Sub address A Data 1 A Data 2 A
Data n A P
4) As the initial state of DAC is not guaranteed, never fail to input the following data in a power on mode.
"06" register: "04"
"00" register: adjustment data
"01" register: adjustment data
"02" register: "00"
"05" register: adjustment data
2. Transmission mode (read mode)
I²C bus protocol
• Slave address: 10110111 (B7H)
• Format
S Slave address R A Data byte
AP
Read
Mode: 1
14