SC8673040L Datasheet, PDF (1/9 Pages) Panasonic Semiconductor – Asymmetric Dual Silicon N-ch Power MOS FET

Doc No. TT4-EA-14212
Revision. 5
SC8673040L
Asymmetric Dual Silicon N-ch Power MOS FET
For DC-DC Converter
Product Standards
MOS FET
SC8673040L
5.1
4.9
8765
Unit : mm
0.22
 Features
 Low Drain-source On-state Resistance : RDS(on) typ.
FET1 : 10 m (VGS = 4.5 V), FET2 : 1.9 m (VGS = 4.5 V)
 Halogen-free / RoHS compliant
(EU RoHS / UL-94 V-0 / MSL : Level 1 compliant)
 Marking Symbol :A2
 Packaging
Embossed type (Thermo-compression sealing) : 3 000 pcs / reel (standard)
1234
0.4
1.0
1.27
1. Gate(FET1) 5. Source(FET2)
2. Drain(FET1) 6. Source(FET2)
3. Drain(FET1) 7. Source(FET2)
4. Drain(FET1) 8. Gate(FET2)
Panasonic
HSO8-F3-B
JEITA
—
 Absolute Maximum Ratings Ta = 25 C
Parameter
Symbol
Rating
FET1 FET2
Unit
Code
—
Internal Circuit
Drain to Source Voltage
VDS
30
30
V
Gate to Source Voltage
Drain Current
Package limited
DC ^*1
Drain Current (Pulsed) ^{*1 *2}
Total Power
Dissipation
Ta = 25 C, DC ^*1
Ta = 25 C, DC ^*3
Tc = 25 C
Thermal
Resistance
Channel to Ambient ^*1
Channel to Ambient ^*3
Channel to Case
Channel Temperature
VGS
ID1
ID2
IDp
PD1
PD2
PD3
Rth(ch-a)1
Rth(ch-a)2
Rth(ch-c)
Tch
20 20
16
46
10
25
48
138
1.7
2.5
1
1
19
40
70
50
125 120
6.6
3.1
150
V
A
A
W
C / W
G2 S2 S2 S2
8
7
6
5
Q2
S1/D2
F^QE¹T1
FET2
1
2
3
4
G1 D1 D1 D1
Pin Name
Operating ambient temperature
Topr -40 to +85 C
Storage Temperature Range
Tstg -55 to +150
Avalanche Current (Single pulse) ^*4
IAR
8
23
A
Avalanche Energy (Single pulse) ^*4
EAR
8
61
mJ
Note *1 Device mounted on a glass-epoxy board in Figure 1.1 and 1.2
1. Gate(FET1) 5. Source(FET2)
2. Drain(FET1) 6. Source(FET2)
3. Drain(FET1) 7. Source(FET2)
4. Drain(FET1) 8. Gate(FET2)
*2 Pulse test : Ensure that the channel temperature does not exceed 150 C
*3 Device mounted on a glass-epoxy board in Figure 1.3
*4 VDD = 24 V, VGS = 10 to 0 V, L = 0.1 mH, Tch = 25 C (initial)
Outline and Figures
FR4 Glass-Epoxy Board (25.4 mm  25.4 mm  0.8 mm)
S2S2 S2 G2
S1/D2
G1D1D1 ^D1
D1 D1D1 G1
Figure 1.1 (FET1) Figure 1.2 (FET2) Figure 1.3 (FET1, FET2)
Page 1 of 8
Established : 2012-09-14
Revised : 2013-05-29