NP061A3 Datasheet, PDF (1/3 Pages) Panasonic Semiconductor – Silicon PNP epitaxial planar transistor

Composite Transistors
NP061A3
Silicon PNP epitaxial planar transistor
For digital circuits
■ Features
• SSS-Mini type 6-pin package, reduction of the mounting area and
assembly cost by one half
• Maximum package height (0.4 mm) contributes to develop thinner
equipments
■ Basic Part Number
• UNR31A3 × 2
■ Absolute Maximum Ratings T_a = 25°C
Parameter
Symbol Rating
Unit
Collector-base voltage (Emitter open) V_CBO
−50
V
Collector-emitter voltage (Base open) V_CEO
−50
V
Collector current
I_C
−80
mA
Total power dissipation ^*
P_T
125
mW
Junction temperature
T_j
125
°C
Storage temperature
T_stg −55 to +125 °C
Note) _*: Measuring on substrate at 17 mm × 10 mm × 1 mm
0.12^+-00..0023
6
5
4
1
2
3
(0.35) (0.35)
1.00±0.05
Display at No.1 lead
Unit: mm
0 to 0.02
1: Emitter (Tr1)
2: Emitter (Tr2)
3: Base (Tr2)
4: Collector (Tr2)
5: Base (Tr1)
6: Collector (Tr1)
SSSMini6-F1 Package
Marking Symbol: 1P
Internal Connection
6 54
Tr1
Tr2
■ Electrical Characteristics T_a = 25°C ± 3°C
123
Parameter
Symbol
Conditions
Min Typ Max Unit
Collector-base voltage (Emitter open)
Collector-emitter voltage (Base open)
Collector-base cutoff current (Emitter open)
Collector-emitter cutoff current (Base open)
Emitter-base cutoff current (Collector open)
Forward current transfer ratio
h_FE Ratio ^*
Collector-emitter saturation voltage
Output voltage high-level
Output voltage low-level
Input resistance
Resistance ratio
Transition frequency
V_CBO
V_CEO
I_CBO
I_CEO
I_EBO
h_FE
h_FE(Small
/Large)
V_CE(sat)
V_OH
V_OL
R₁
R₁ / R₂
f_T
I_C = −10 µA, I_E = 0
I_C = −2 mA, I_B = 0
V_CB = −50 V, I_E = 0
V_CE = −50 V, I_B = 0
V_EB = −6 V, I_C = 0
V_CE = −10 V, I_C = −5 mA
V_CE = −10 V, I_C = −5 mA
I_C = −10 mA, I_B = − 0.3 mA
V_CC = −5 V, V_B = − 0.5 V, R_L = 1 kΩ
V_CC = −5 V, V_B = −3.5 V, R_L = 1 kΩ
V_CB = −10 V, I_E = 1 mA, f = 200 MHz
−50
−50
80
0.50
−4.9
−30%
0.8
− 0.1
− 0.5
− 0.1
0.99
− 0.25
− 0.2
47 +30%
1.0 1.2
80
V
V
µA
µA
mA


V
V
V
kΩ

MHz
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.
2. _*: Ratio between one and another
Publication date: July 2003
SJJ00258BED
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