MN3306 Datasheet, PDF (1/5 Pages) Panasonic Semiconductor – 128-Stage Ultra Low Voltage Operation BBD for Audio Signals

MN3300 Series
MN3306
128-Stage Ultra Low Voltage Operation BBD for Audio Signals
s Overview
The MN3306 is a 128-stage ultra low voltage operation BBD variable
delay line in audio frequency range. The device operates on +3V
supply and provides a signal delay up to 6.4 ms and is suitable for
use as reverberation effect of low voltage operation audio equipment
such as portable stereo, radio cassette recorder and microphone.
s Features
• Variable signal delay of the audio signal : 0.064 to 6.4 ms
• Wide range of supply voltage : 1.8 to 5.0 V
• No insertion loss : L_i=0 dB typ.
• Wide dynamic range : S/N=79 dB typ.
• Low distortion : THD=0.3 % typ. (V_i=0.22 V_rms)
• Clock frequency range : 10 to 200 kHz (1.8 V≤V_DD<4.0 V)
10 kHz to 1 MHz (4.0 V≤V_DD≤5.0 V)
• N-channel 2-layer silicon gate process
• 8-Pin Dual-In-Line Plastic Package
s Applications
• Reverberation and echo effects of audio equipment such as radio
cassette recorder, car radio, portable radio, portable stereo, echo
microphone and Karaoke machine, etc.
• Sound effect of electronic musical instruments
• Variable or fixed delay of analog signals
s Pin Assignment
GND
CP2
IN
V_DD
1
8
2
7
MN3306
3
6
4
5
V_D2
OUT
CP1
V_D1
DIP008-P-0300
s Block Diagram
IN ³
128-Stage
BBD
8 _VD2
7
OUT
5
V_D1
s Pin Descriptions
Pin No. Symbol
1 GND
2
CP2
3
IN
4
V_DD
5
V_D1
6
CP1
7
OUT
8
V_D2
Pin Name
Ground pin
Clock input 2
Signal input pin
V_DD apply pin
V_D1 apply pin
Clock input 1
Output pin
V_D2 apply pin
Description
Connected to ground.
Basic clock pulse is applied to transfer electric charge of BBD.
Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin.
Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse
input gate of the BBD transfer gate.
Furthermore, voltage is supplied to step-up circuit.
The same phase clock pulse as CP1 is applied through capacitor.
Clock pulse of inverted phase to CP2 is applied.
Composed signal of 1024th and 1025th stages is output.
The same phase clock pulse as CP2 is applied through capacitor.
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