MN103E0600YD Datasheet, PDF (1/5 Pages) Panasonic Semiconductor – MN103E0600YD

MN103E0600YD
Type
Instruction Cache
Data Cashe
Package
Minimum Instruction
Execution Time
Interrupts
Timer Counter
DMA Contoroller
Serial Interface
I/O Pins
I/O
Memory Management
Function
On-chip Bus Controller
MN103E0600YD (under development)
16 K-byte (4-way, set-associative)
16 K-byte (4-way, set-associative)
MLGA239-C-1111
7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz)
• XIRQ × 8 • NMI • Timer × 14 • DMAC × 4 • WDT • SIO × 6 • I²C × 2 • Asynchronous bus error
8-bit timer × 4 (all down counters)
Cascade connection possible (usable as a 16/24/32-bit timer)
Timer output possible (Duty = 1:1)
Internal clock source or external clock source selectable
Selectable as a serial interface clock
16-bit timer × 7 (down counters)
Cascade connection possible (usable as a 32-bit timer)
Timer output possible (Duty = 1:1)
Internal clock source or external clock source selectable
Partially selectable as a serial interface clock
16-bit timer × 1 (up counter)
Internal clock source or external clock source selectable
Input capture function (rising edge, falling edges, or both selectable)
PWM generating function (compare/capture register × 2 contained)
Watchdog timer × 1
Number of channels: 4
Transfer unit: 1/2/4/16 byte
Maximum number of bytes transferred: 1Mbyte
Start factor: External request, interrupt, software
Transfer mode: 2-bus cycle transfer
Transfer mode: Batch transfer, intermittent transfer
Addressing mode:
Source/destination each fixed, increment/decrement specification possible
Increment/decrement automatically executed according to the transfer unit
UART/synchronous (co-used) × 2-ch.
UART (with CTS control) × 1-ch.
19 • Common use : 19
32-entry full-associative TLB loaded (instructions/data separated from each other)
Address conversion by paging (page size: 1 K-byte. 4 K-byte, 128 K-byte, 4 M-byte variable)
Concurrent access from three types of master devices to four types of slave devices possible
MAF00011BEM