MN102L610B Datasheet, PDF (1/3 Pages) Panasonic Semiconductor – RESET Watchdog Timer counter 0 to 5 Timer counter 6 to 7

MN102L610B
Type
ROM (×8-bit / ×16-bit)
RAM (×8-bit / ×16-bit)
Package
Minimum Instruction
Execution Time
Interrupts
Timer Counter
Serial Interface
I/O Pins
I/O
A/D Inputs
PWM
Special Ports
Notes
1
MN102L610B
External
4K
LQFP100-P-1414 ^*Lead-free
88.5 ns (at 4.5 V to 5.5 V, 22.6 MHz)
• RESET • Watchdog • Timer counter 0 to 5 • Timer counter 6 to 7
• Timer counter 6 to 7 compare capture A • Timer counter 6 to 7 compare capture B
• ATC transfer finish • External 0 to 4 • Serial ch.0, 1 transmission • Serial ch.0, 1 reception
• NMI pin • A/D conversion finish
Timer counter 0 : 8-bit × 1 (timer output, event count)
Clock source ····················· 1/1, 1/128 of system clock frequency; 1/4 of low speed clock frequency;
external clock
Interrupt source ················ underflow of timer counter 0
Timer counter 1 : 8-bit × 1 (timer output, event count, A/D conversion start up)
Clock source ····················· system clock; 1/4 of low speed clock frequency; external clock;
timer counter 0 output
Interrupt source ················ underflow of timer counter 1
Timer counter 2 to 3 : 8-bit × 1 (timer output, event count, UART baud rate generator)
Clock source ····················· system clock; external clock; timer counter 0 output;
timer counter 1, 2 output
Interrupt source ················ underflow of timer counter 2, 3
Timer counter 4, 5 : 8-bit × 1 (timer output, event count)
Clock source ····················· 1/4 of low speed clock frequency; external clock; timer counter 0 output;
timer counter 3, 4 output
Interrupt source ················ underflow of timer counter 4, 5
Timer counter 6, 7 : 16-bit × 1
(timer output, event count, input capture, output compare, PWM output, 2-phase encoder input)
Clock source ····················· system clock; external clock; timer counter 4, 5 output
Interrupt source ················ coincidence with compare capture A or at capture; coincidence with compare
capture B or at capture; underflow of timer counter 6, 7
Connectable timer counter 0 to 5
Serial 0 : 7, 8-bit × 1 (common use with UART, transfer direction of MSB/LSB selectable)
Clock source ····················· 1/16 of timer counter 2 frequency; 1/16 of timer counter 3 frequency;
external clock; 1/2 of timer counter 2 frequency
Serial 1 : 7, 8-bit × 1 (common use with UART, transfer direction of MSB/LSB selectable)
Clock source ····················· 1/16 of timer counter 2 frequency; 1/16 of timer counter 3 frequency;
external clock; 1/2 of timer counter 3 frequency
UART × 2 (common use with serial 0, 1)
I²C × 2 (single master)
80 • Common use : 16 (by 8 bits), 8 (by 4 bits), 56 (by bit)(MN102LF61G)
48 • Common use : 8 (by 4 bits), 40 (by bit)(MN102L610B)
8-bit × 8-ch. (with S/H)
16-bit × 2-ch.
LED drive port × 2
Burst ROM inferface support, ATC (between serial 0ch and internal RAM) support
MAE00004CEM